Other

Masahiro Yoshida

Yutaka Akiyama

Kanji Otsuka

Yoichi Sato

Shigeru Yamamoto

Tsuneo Ito

Yuko Tanba

Takeshi Koyama

A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memoriesincluding basic cellsarranged in a cluster, the basic cellincluding a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memorieslocated along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibusincluding a through-via, an arbitrary one of the basic cellsis directly accessed through the multibusfrom the controller chip so that truth value data is written therein, and whereby the arbitrary basic cellis switched to a logic circuit as conjugate.

Memory/logic conjugate system

Growing community of inventors

Hamura, Japan

Masahiro Yoshida