Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Vlsi Engineering Corporation

Hitachi Ltd., and Hitachi Vlsi Engineering Corp.

Masahiro Yoshida

Katsuyuki Sato

Sadayuki Ohkuma

Masahiro Ogata

Miki Matsumoto

Kanji Oishi

Osamu Nagashima

Hitoshi Kawaguchi

Yasunori Yamaguchi

Makoto Morino

Yosuke Yukawa

Tetsuya Saeki

Jun Mitake

Terutaka Okada

A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

Semiconductor memory device

A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features include a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

A semiconductor memory is provided with a first memory cell group, a second memory cell group, a first register for a serial output operation for holding information related to the first memory cell group, a second register for a serial output operation for holding information related to the second memory cell group, and transfer means for transferring information related to either the first or second memory cell group to either the first or second serial output register. By virtue of this arrangement, while the information transferred to the first serial output register is being serially output therefrom, information can simultaneously be transferred to the second serial output register by the transfer means.

Dynamic ram

The semiconductor memory device includes at least two memory arrays, a first selection circuit which selects a memory cell from either one of the memory arrays in accordance with address signals, preferably two spare memory arrays and a second selection circuit which selects a memory cell from either one of the spare memory arrays. If a defective memory cell or cells are contained in one of the two memory arrays, the second selection circuit can select a spare memory cell or cells from any of the two spare memory arrays in place of the defective memory cell or cells. Thus, the spare memory arrays can be used effectively. Two sets of main amplifiers are also disposed and only one of them, which receives the data from the memory cell selected from the memory arrays or spare memory arrays, is operated. Thus, lower power consumption can be realized.

Semiconductor memory device having redundancy means

The semiconductor memory device includes at least two memory arrays, a first selection circuit which selects a memory cell from either one of the memory arrays in accordance with address signals, preferably two spare memory arrays and a second selection circuit which selects a memory cell from either one of the spare memory arrays. If a defective memory cell or cells are contained in one of the two memory arrays, the second selection circuit an select a spare memory cell or cells from any of the two spare memory arrays in place of the defective memory cell or cells. Thus, the spare memory arrays can be used effectively. Two sets of main amplifiers are also disposed and only one of them, which receives the data from the memory cell selected from the memory arrays or spare memory arrays, is operated. Thus, lower power consumption can be realized.

Growing community of inventors

Tachikawa, Japan

Masahiro Yoshida