Fujitsu Corporation

Masahiro Yanagida

Hiroyuki Fujimoto

Hiromasa Takahashi

Hidenobu Ohta

Hitoshi Yamanaka

Shuntaro Fujioka

Shinichi Moriwaki

Osamu Tachibana

A semiconductor device includes a plurality of built-in memories, and each of the built-in memories includes a plurality of memory cells. Each built-in memory includes a selector circuit that connects a selected memory cell among the memory cells to an outside, a memory cell relief circuit that, when a fault has occurred in one of the memory cells, transmits, to the selector circuit, a relief signal configured to connect a normal memory cell to the outside without connecting the one of the memory cells in which the fault has occurred, to the outside, and switches selection in the selector circuit, and an abnormality detection circuit that performs abnormality detection for the memory cell relief circuit, based on a temporal change in the relief signal output from the memory cell relief circuit.

Semiconductor device including abnormality detection circuit and semiconductor device control method for detecting abnormality

An integrated circuit includes a storing unit; and a tester that executes a write and read test on the storing unit based on received test information including a pair of address and data, the tester including: a first retain unit that retains, when a write is made based on the test information, the first write address and the first write data used in the write; a first generator that generates, based on the first write address retained in the first retain unit, a first read address used for reading first read data from the first read address in the storing unit simultaneously with writing second write data to a second write address based on the test information; and a second generator that generates, based on the first write data retained in the first retain unit, an expected value of the first read data.

Integrated circuit, test circuit, and method of testing

A processor includes an arithmetic device, a storage device that holds arithmetic data, a data generator that generates test data, an address generator that generates an address at which the test data is to be written, a test data number counter that counts a number of test data, an error information holder that holds mismatch error information, an error occurrence bit position holder that holds a position of a bit at which a mismatch error has occurred, an error occurrence test data number holder that holds number of test data counted by the test data number counter, and a comparator that compares test data written to the storage device with test data read from the storage device and stores error information in the error information holder and a position of a bit and number of the test data in which the mismatch error has occurred.

Processor and method for controlling storage-device test unit

A storage circuit, an integrated circuit and a scanning method are provided. The storage circuit includes a first storage element, and a second storage element connected to an output of the first storage element. The storage circuit includes a first setting circuit that is configured to set data of a first logic value to the first storage element when a clear signal is applied, and a second setting circuit that is configured to set data of a second logic value to the second storage element and transmit the second logic value data to a different storage circuit when a second clock signal is in an off state and the clear signal is applied.

Storage circuit, integrated circuit, and scanning method

A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the pipeline operation device, a pipeline operation unit that can perform a pipeline operation, a non-pipeline operation unit that cannot perform a pipeline operation, and a register that is shared by the pipeline operation unit and the non-pipeline operation unit are arranged. To perform an operation while an operation result of each of the pipeline units is being written into the register, translating an instruction to the pipeline operation unit is interlocked when the writing of the operation result of the pipeline operation unit overlaps with the writing of the operation result of the non-pipeline operation unit. The pipeline operation method and the pipeline operation device are applicable to a computing system where plural operation units including pipeline operation units and non-pipeline operation units share one writing port to perform an arithmetic operation.

Pipeline operation method and pipeline operation device to interlock the translation of instructions based on the operation of a non-pipeline operation unit

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Kawasaki, Japan

Masahiro Yanagida