Hitachi, Ltd.

Pioneer Electronic Corporation

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Hokkai Semiconductor Ltd.

Masahiro Yamamura

Yutaka Kobayashi

Hideaki Uchida

Kiyoo Itoh

Takao Watanabe

Ryoichi Hori

Goro Kitsukawa

Katsuhiro Shimohigashi

Takahide Ikeda

Noriyuki Homma

Shinji Nakazato

Nobuo Tanba

Yoshikazu Saito

Yasuo Kominami

Katsuji Mizumoto

Toshihide Hanada

Masahiro Iwamura

Tatsumi Yamauchi

Nozomu Matsuzaki

Atsushi Hiraishi

Kazuo Watanabe

Takashi Akioka

Yuji Yokoyama

Masanori Ienaka

Akira Ide

Nobuyuki Gotou

Kiyoshi Inoue

Hirotaka Nishizawa

Toshio Sugano

Toshio Yamada

Masamichi Ishihara

Hidetoshi Iwai

Yasunori Yamaguchi

Jiro Sawada

Seiichiro Tsukui

Tadao Kaji

Takashi Araki

Noboru Shiozawa

Yoshio Sakamoto

Shinobu Takeura

Norihiko Kasai

Ichirou Anjou

Yoshikasu Saito

Masakatsu Goto

Yoshiaki Anata

Yasushi Sekine

Tetsuji Kohara

Sadao Morita

Tomoyoshi Miura

Mutsuo Tsukuda

Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

Semiconductor memory device

Semiconductor integrated circuit device, and process and apparatus for

A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

Signal transition detector circuit

A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

Semiconductor device

Semiconductor memory device having separately biased wells for isolation

Semiconductor CMOS memory device with separately biased wells

Semiconductor memory device having bipolar transistor and structure to

An output from an OCL type power output circuit is applied to a loudspeaker load through a switching means such as a relay. A first detector circuit and a second detector circuit detect a first operating status (e.g., output d.c. level) and a second operating status (e.g., output current level of an output transistor) of the OCL type power output circuit, respectively. The detection output signals of the first detector circuit and the second detector circuit are respectively applied to a first detecting transistor and a second detecting transistor. In the normal operation status of the OCL type power output circuit, the first detecting transistor and the second detecting transistor are respectively biased into 'on' states by the first detector circuit and the second detector circuit so as to permit predetermined currents to flow. When the first and second detecting transistors are in their 'on' states they control a driving transistor into an 'on' state. Then, the switching means, such as a relay, is controlled into a closed state. In the abnormal operation status of the OCL type power output circuit, the first detector circuit or the second detector circuit controls the first detecting transistor or the second detecting transistor into an 'off' state, so that the switching means, such as a relay, is controlled into an open state.

Power output circuit

This invention relates to a constant voltage output circuit using, as its reference potential source, power source feed terminals for feeding a power source voltage to a reference potential source of a given circuit. The constant voltage output circuit includes a series circuit of an npn transistor and a pnp transistor interposed between the reference potential source of the given circuit and the power source feed terminals, means for biasing the base potential of the pnp transistor by a predetermined potential with respect to the potential of the power source feed terminals, and an emitter follower circuit disposed in the collector output circuit of the npn transistor of the series circuit, and forming a negative feed-back circuit.

Constant voltage output circuit

The output derived from an electric circuit such as an OCL type power amplifier circuit is delivered to a load such as a speaker, through a switching means such as a relay. When the operation of the electric circuit has come out of a predetermined range of operation, the switching means is operated to break the connection between the electric circuit and the load. A detection circuit for detecting the operation of the electric circuit includes a detecting transistor constructed in a semiconductor integrated circuit. The detecting transistor is connected at its base to the input terminal for external connection of the semiconductor integrated circuit, so as to receive a signal representative of the operation state of the electric circuit. The detecting transistor is so biased as to allow a predetermined electric current to flow therethrough, when the electric circuit is operating within the predetermined range of operation. However, in case of a breakdown of the detecting transistor, or when the operation of the electric circuit has come out of the predetermined range of operation, the current flowing through the detecting transistor is changed from the predetermined level. This change is transmitted to a driving transistor which is adapted to break the switching means such as a relay.

Protective circuit

The present invention is related to a temperature-compensated circuit for controlling the drive of a motor, comprising a differential comparator for comparing a running-speed signal of a motor with a reference signal, and a feedback amplifier having a differential amplifier to which is given an input offset.

Circuit for controlling the drive of motor

A differential amplification is disclosed which comprises differential paired transistors. The direct bias current flowing in the differential paired transistors is determined by a constant current flowing from a first constant current circuit connected to the emitters of the differential paired transistors. The collector current of one of the differential paired transistors is caused to flow as an input current in a high-precision current mirror circuit. The current value of the constant current flowing in the first constant current circuit is set at 2Io. Since a direct base current Ib flows in the differential paired transistors, the current value of the collector current of one of the differential paired transistors is (Io-Ib). Accordingly, the high-precision current mirror circuit generates an output current of a current value of (Io-Ib) at the output terminal thereof. The differential amplification circuit includes a second constant current circuit having a current value Io corresponding to 1/2 of the current value of the constant current flowing in the first constant current circuit. A bias transistor is connected between the high-precision current mirror circuit and the second constant current circuit, and the direct base current Ib flows in this bias transistor. Accordingly, in the equilibrium state between the differential paired transistors, the output current appearing at the output terminal of the high precision current mirror circuit becomes zero, and the offset output current can be eliminated or moderated.

Differential amplification circuit

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Takasaki, Japan

Masahiro Yamamura