Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Tokyo Electronics Co., Ltd.

Masahiro Ushiyama

Toshiyuki Mine

Jiro Yugami

Takashi Kobayashi

Shimpei Tsujikawa

Hitoshi Kume

Tokuo Kure

Tetsuo Adachi

Hiroshi Kawakami

Tsuyoshi Fujiwara

Yuzuru Ohji

Katsuhiko Ichinose

Naohumi Ohashi

Tetsuo Saito

In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride filmfor self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400&#xb0; C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride filmconstituting a passivation film is formed at a substrate temperature of about 350&#xb0; C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride filmis smaller than that contained in the silicon nitride film, making it possible to suppress hydrogen release from the silicon nitride film

Semiconductor integrated circuit device and process for manufacturing the same

The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric filmis made as follows: after forming a silicon nitride filmwith a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxideon the silicon nitride film, then this silicon oxideis completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride filmin the gate dielectric filmwhose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.

Semiconductor device and production method thereof

Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.

Semiconductor device having thin electrode laye adjacent gate insulator and method of manufacture

The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film is made as follows: after forming a silicon nitride film with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide on the silicon nitride film , then this silicon oxide is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film in the gate dielectric film whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.

Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture

Provided is an improved fabrication process for a semiconductor device by means of which in fabrication of insulated gate semiconductor devices having gate insulating films including silicon oxide films of different thickness, no contamination from a photoresist is ensured in a silicon oxide film, generation of defects in the silicon oxide film to be otherwise caused by aqueous solution treatments is suppressed, and thereby variability of characteristics among the semiconductor devices is suppressed. A silicon oxide film of a gate insulating film is formed on a semiconductor surface, a silicon nitride film is formed thereon by means of a chemical vapor deposition method using monosilane and ammonia as a source gas prior to formation of a resist film, the resist film is selectively formed on the surface, part of the silicon nitride film not covered by the resist film and the silicon oxide film therebeneath are removed to expose a semiconductor surface, the exposed semiconductor surface is oxidized to form a second silicon oxide film having a thickness different from that of the previously described silicon oxide film, and gate electrodes are formed on the respective insulating films.

Fabrication process for semiconductor device

Semiconductor device having thin electrode layer adjacent gate insulator

Before a high permittivity interlayer insulating film of a non-volatile memory having a two-level gate electrode structure, a surface of a substrate in a peripheral circuit MOS area is successively covered with a thermal oxide film and a polycrystalline silicon film. Before the interlayer insulating film is selectively removed on the peripheral circuit MOS area, the surface of the interlayer insulating film of the non-volatile memory is covered with a polycrystalline silicon film. When the interlayer insulating film in the peripheral circuit MOS area is removed, the polycrystalline silicon film as a lower layer in the peripheral circuit area serves as a buffer layer against contamination or damage due to the etching, and the conductive layer on the surface of the interlayer insulating film in the non-volatile memory portion also serves as a buffer layer against the contamination or damage due to the etching.

Manufacturing method of non-volatile semiconductor memory device

Growing community of inventors

Kokubunji, Japan

Masahiro Ushiyama