Sanyo Electric Co., Ltd.

Tokyo University of Science

Masahiro Umewaka

Hiroya Yamamoto

Keiji Morijiri

Keitaro Sekine

Akira Hyogo

Masaaki Suzuki

Keitarou Sekine

Shinji Osugi

Akira Hyougo

To provide a receiver having a plurality of receiver circuits respectively connected to different antennas and a selecting circuit for selecting a receiver circuit whose receiving level is equal to a predetermined threshold value or a receiver circuit whose receiving level is higher than the predetermined threshold value as a main processing circuit to bring at least some of the receiver circuits other than the selected receiver circuit into a non-operation state.

Receiver

A demodulation circuit for demodulating an FSK signal comprising a long bit having a long bit period and a short bit having a short bit period comprises a bit boundary detection section for detecting a bit boundary timing of each bit, and a bit determination section for making determination for each bit such that a particular bit is determined to be a long bit when a threshold time period has passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit, and a particular bit is determined to be a short bit when the threshold time period has not passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit.

FSK signal demodulation circuit

There is disclosed a tuning circuit having a coil and a capacitor comprises a resistance-adjustment circuit connected in parallel with the coil and the capacitor. The resistance-adjustment circuit changes a resistance of the tuning circuit when resonant. The resistance-adjustment circuit comprises a series circuit of a resistor and a switching element having an ON-resistance smaller than the resistance of the resistor, and turning on/off the switching element causes the resistance of the tuning circuit when resonant to change.

Tuning circuit with amplitude attenuation function and integrated circuit for radio communication apparatus

In some examples, a hysteresis comparator includes a series resistor portion including a plurality of resistors for dividing a power supply voltage, the series resistor portion generating a first midpoint voltage and a second midpoint voltage higher than the first midpoint voltage, a first comparator configured to compare the first midpoint voltage and a reference voltage, a second comparator configured to compare the second midpoint voltage and the reference voltage, and a flip-flop having a clock terminal to which an output signal of the first comparator is applied and a reset terminal to which an output signal of the second comparator is applied. In some examples, a hysteresis comparator further includes an OR gate to which output signals of the first comparator and the second comparator are applied, and an AND gate to which output signals of the first comparator and the second comparator are applied.

Hysteresis comparator and reset signal generator

A tuning circuit having an amplitude-varying function is disclosed that comprises a coil, a capacitor, and a resistance-adjusting element connected in parallel to the coil and the capacitor for varying resistance at time of resonance of the tuning circuit, wherein the amplitude of an output signal of the tuning circuit is varied by varying the resistance with the resistance-adjusting element.

Tuning circuit having amplitude-varying function

A volume/tone control circuit comprises first and second latch circuits (8) and (9) for latching the volume control data BD and the tone control data TD stored in the shift register (7); a volume regulating circuit (2) and a tone regulating circuit (3) for regulating the volume and the tone of the input audio signal according to the respective output data of the first and second latch circuits (8) and (9); and a zero-crossing detection circuit (12) for detecting zero-crossings of the input signal. The input audio signal is fed to the zero-crossing detection circuit (12) when a data detection circuit (20) detects that the input data and the output data of the first latch circuit (8) differ. The output audio signal of the tone regulating circuit is fed to the zero-crossing detection circuit (12) when the input data and the output data of the second latch circuit (9) differ and they control data of either the first latch circuit or the second latch circuit is updated in response to the detection output of the zero-crossing detection circuit.

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Ota, Japan

Masahiro Umewaka