Sharp Kabushiki Kaisha Corporation

Masahiro Tomida

Naoki Ueda

Kaoru Yamamoto

Yasuyuki Ogawa

Akihiro Oda

An active matrix substrate of an embodiment includes a plurality of TFTs provided in a peripheral circuit region. The plurality of TFTs includes a TFT (A) in which, when viewed in a direction perpendicular to a substrate (A), a length in the channel width direction of a source electrode region (AR) and a length in the channel width direction of a drain electrode region (AR), WAs and WAd, are each smaller than a length in the channel width direction of the oxide semiconductor layer (A), WAos, the length in the channel width direction of the oxide semiconductor layer (A), WAos, is smaller than a length in the channel width direction of a gate electrode (A), WAg, and a region in which at least one of the source electrode region (AR) and the drain electrode region (AR) is in contact with the oxide semiconductor layer(A) entirely overlaps the gate electrode (A).

Active matrix substrate and liquid crystal display panel comprising same

An active matrix substrate includes a display region in which a plurality of pixels are provided and a frame region lying outside the display region. The frame region includes a plurality of peripheral circuit TFTs which are supported by a substrate and which are constituents of a driving circuit. Each of the plurality of peripheral circuit TFTs includes a gate electrode, an oxide semiconductor layer arranged so as to at least partially extend over the gate electrode but to be insulated from the gate electrode, and source and drain electrodes connected with the oxide semiconductor layer.

Active matrix substrate

A display device includes: a display unit, a driver unit, and a control unit. The display unit includes a plurality of pixel units arranged in a matrix. The driver unit includes an output transistor configured to drive a plurality of scanning lines connected to the plurality of pixel units. The control unit is configured to supply to the driver unit in a display period, a signal for displaying an image on the display unit, and control a bias state of the output transistor in a display suspension period, so that an absolute value of a threshold voltage of the output transistor which is increased in the display period decreases.

Display device and driving method thereof

A shift register circuit has a plurality of unit circuits that are cascade-connected to one another and that output received pulse signals as output signals in accordance with a clock signal, the shift register circuit sequentially outputting the output signals from the plurality of respective unit circuits. The output circuits each include a double-gate transistor having first gate electrode that controls conductivity between the drain electrode and the source electrode, and a second gate electrode formed through an insulating layer and disposed to face the first gate electrode across a semiconductor layer between the drain electrode and the source electrode. The shift register circuit applies a prescribed voltage to the second gate electrode in accordance with a voltage applied to the first gate electrode.

Shift register circuit, drive circuit, and display device

An active matrix substrate () includes a display region (R) in which a plurality of pixels are provided and a frame region (R) provided around the display region, the frame region including a plurality of peripheral circuit TFTs () which are constituents of a driving circuit, wherein each of the plurality of peripheral circuit TFTs includes a gate electrode (), a source electrode (), a drain electrode (), and an oxide semiconductor layer (), and in at least some of the plurality of peripheral circuit TFTs, a source connecting region (Rs) that is a connecting region between the oxide semiconductor layer and the source electrode and a drain connecting region (Rd) that is a connecting region between the oxide semiconductor layer and the drain electrode are asymmetrically provided.

The area Cof the channel region of the drive TFT and the area Cof the channel region of the memory TFT are set to have a relationship C&#x3c;Cto an extent that allows predetermined hysteresis natures dependent on respective functions thereof.

Thin film transistor memory and display unit including the same

A nonvolatile semiconductor memory device and its writing method for reducing a writing rate variation without changing a voltage condition applied for each memory cell in writing operation is provided. The device comprises a memory cell array configuration where each drain of the memory cells on the same column is connected to a first bit line via a second bit line and a bit line contact, and the shortest distance from each drain of the memory cells to the bit line contact varies according to a location of the memory cell in the column direction. The method includes a writing operation carried out sequentially from the nearest memory cell to the bit line contact, upon writing continuously so that the memory cell current becomes small for all or some of the memory cells on the same column between the two adjacent bit line contacts in the column direction.

Growing community of inventors

Osaka, Japan

Masahiro Tomida