Seiko Epson Corporation

Fujikoshi Machinery Corp.

Fujikoshi Kikai Kogyo Kabushiki Kaisha

Masahiro Takeuchi

Takafumi Noda

Takashi Kumagai

Satoru Kodaira

Yoshio Nakamura

Makoto Nakajima

Yasuhide Denda

Yasunobu Tokuda

Satoru Arakawa

Harumichi Koyama

Satoki Kanda

Mitsue Ogawa

Toshihisa Yanagisawa

Toshiaki Seki

Masanori Fukushima

Yoichi Morozumi

A liquid ejecting head with a supply port and an outlet port includes a pressurization chamber communicating with one of the suplly port and the outlet port, a first flow path communicating with the pressurization chamber and extending in a first axial direction, a second flow path communicating with the other of the supply port and the outlet port and extending in a second axial direction orthogonal to the first axial direction, and a nozzle that is provided to branch from the second flow path and that discharges the liquid along the first axial direction. When viewed in a third axial direction orthogonal to the first axial direction and the second axial direction, an inner wall at a location at which the second flow path and the first flow path intersect includes an inclined surface inclined with respect to the first axial direction and the second axial direction.

Liquid ejecting head, method for manufacturing liquid ejecting head, and liquid ejecting system

The double face polishing apparatus is capable of controlling an amount of supplying slurry to a lower polishing plate. The double face polishing apparatus comprises: a lower polishing plate and an upper polishing plate; a carrier provided between the polishing plates, the carrier having a through-hole for holding a workpiece; a plate driving unit for rotating the polishing plates; a carrier driving unit for rotating the carrier; ring-shaped ducts coaxially provided to the upper polishing plate; a slurry supply source supplying slurry to the ring-shaped ducts; and supply pipes for supplying the slurry to the lower polishing plate. The slurry is supplied to each of coaxial polishing zones of the lower polishing plate via the corresponding ring-shaped ducts and the supply pipes.

Double face polishing apparatus

A semiconductor device having trench isolation regions in which leaks are suppressed may be formed using the following steps. (a) Forming a trenchin a semiconductor layer(b) forming a dielectric layerthat fills the trenchand (c) conducting a thermal treatment of the dielectric layerwherein the thermal treatment is conducted at temperatures of 1050&#xb0; C. or higher.

Methods for manufacturing semiconductor devices and semiconductor devices having trench isolation regions

A semiconductor device includes an SRAM section and a logic circuit section formed on a single semiconductor substrate. First and second gate electrode layers located in a first conductive layer, first and second drain-drain contact layers located in a second conductive layer, first and second drain-gate contact layers located in a third conductive layer become conductive layers for forming a flip-flop of the SRAM section. The logic circuit section has no wiring layer at the same level as the first and second drain-drain contact layers.

Semiconductor device

A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.

Semiconductor device with SRAM section including a plurality of memory cells

The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain&mdash;drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. The drain-gate connection layer has an extension section extending in a direction toward the drain-gate connection layer. The drain-gate connection layer has an extension section extending in a direction toward the drain-gate connection layer.

Semiconductor memory device

The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain&mdash;drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. Driver transistors of one memory cell do not commonly share the n&plus; type source region with driver transistors of another memory cell.

Static RAM semiconductor memory device having reduced memory

The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define connection wirings of a flip-flop. A p type well contact region is provided for every two of the memory cells arranged in the Y-axis direction.

First and second gate electrode layers located in a first conductive layer, first and second drain-drain connecting layers located in a second conductive layer, and first and second drain-gate connecting layers located in a third conductive layer become conductive layers for forming a flip-flop. First and second contact-conductive sections are formed in a region from an interlayer dielectric between the first and second conductive layers to an interlayer dielectric between the second and third conductive layers. The first drain-gate connecting layer is connected to the second gate electrode layer with the first contact-conductive section interposed. The second drain-gate connecting layer is connected to the first gate electrode layer with the second contact-conductive section interposed.

The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. A source contact layer of load transistors are located adjacent end sections of the gate electrode layers, and both of the end sections bend outwardly to avoid contact with the source contact layer.

Semiconductor memory device having different distances between gate electrode layers

First and second gate electrode layers that are positioned in a first conductive layer, first and second drain-drain contact layers that are positioned in a second conductive layer, and first and second drain-gate contact layers that are positioned in a third conductive layer together form conductive layers for a flip-flop. A sub word line extends in the X-axis direction in the first conductive layer. A V wire is disposed extending in the X-axis direction in the second conductive layer. A main word line is disposed extending in the X-axis direction in the third conductive layer. A bit line, a bit line/, a V wire, and a V wire are disposed extending in the Y-axis direction in the fourth conductive layer.

Semiconductor memory device having improved pattern of layers and compact dimensions

The drain of a drive transistor Q and the drain of a load transistor Q are connected by a first drain&mdash;drain contact layer. The drain of a drive transistor Q and the drain of a load transistor Q are connected by a second drain&mdash;drain contact layer. The gate electrodes of the drive transistor Q and the load transistor Q (a first gate electrode layer) are connected to the second drain&mdash;drain contact layer by a first drain-gate contact layer. The gate electrodes of the drive transistor Q and the load transistor Q (a second gate electrode layer) are connected to the first drain&mdash;drain contact layer by a second drain-gate contact layer.

Semiconductor memory device having gate electrode, drain-drain contact, and drain-gate contact layers

A semiconductor memory device comprising first and second gate electrode layers in a first conductive layer, first and second drain-drain connecting layers in a second conductive layer, and first and second drain-gate connecting layers in a third conductive layer. The first and second drain-gate connecting layers are located higher than the first and second gate electrode layers. Therefore, a source contact layer can be located in the region between gate electrode layers while preventing a contact with the second drain-gate connecting layer.

In the polishing system of the present invention, a adhering unit adheres a wafer on a carrying plate using liquid. A polishing unit polishes the wafer using a polishing plate. A feeding unit conveys the carrying plate from the adhering unit to the polishing unit. A dismounting unit removes the wafer from the carrying plate. A first discharging unit conveys the carrying plate from the polishing unit to the dismounting unit. A cleaning unit cleans the vacant carrying plate. A second discharging unit conveys the carrying plate from the dismounting unit to the cleaning unit. A third discharging unit conveys the carrying plate from the cleaning unit to the adhering unit. The units are formed into a loop lines so that the carrying plate is circulated in the loop line and the wafers are polished therein.

Polishing system for polishing wafer

A first word line connects the gate electrodes of first transfer transistors in adjacent memory cells. A second word line connects the gate electrodes of second transfer transistors in adjacent memory cells. A ground line connects the source regions of first and second driver transistors. The first and second word lines and ground line are formed by a wiring layer different from the wiring layer that forms the gate electrodes of the first and second transfer transistors. The ground line shields the first and second driver transistors, TFTs and the like. Drain contacts include chamfered sides between which the ground line is disposed.

Growing community of inventors

Chino, Japan

Masahiro Takeuchi