Kabushiki Kaisha Toshiba

Other

Skhynix Inc.

Toshiba Memory Corporation

Masahiro Takahashi

Dong Keun Kim

Tsuneo Inaba

Akira Katayama

Ji Wang Lee

Hyuck Sang Yim

Byoung Chan Oh

Ryousuke Takizawa

A semiconductor memory device comprises a first memory cell with a first variable resistance element. A first write controller is configured to write data into the first memory cell using a first voltage that is supplied via a first wiring. A second write controller configured to write data into the first memory cell using a second voltage that is lower than the first voltage when the first voltage supplied via the first wiring is reduced below a threshold level.

Semiconductor memory device

According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.

Resistance change memory

According to one embodiment, a semiconductor memory device includes a first memory cell array including a first memory cell having a variable resistive element, a second memory cell array including a second memory cell having the variable resistive element, a reference signal generation circuit which generates a reference signal, a sense amplifier having a first input terminal and a second input terminal, and a read enable control circuit which generates a read enable signal in accordance with a command from outside and control switching between a single cell read mode and a twin cell read mode.

According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.

Memory device

A semiconductor storage device includes a first bit line and a second bit line. A nonvolatile memory element and a first cell transistor are connected in series between the first bit line and the second bit line. A sense transistor has a gate connected to a sense node which is provided between the first bit line and the memory element. A read bit line is connected to a source or a drain of the sense transistor. The read bit line is configured to transmit data of the memory element. A sense amplifier is configured to detect the logic of data transmitted from the read bit line.

Semiconductor storage device

According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

According to one embodiment, a resistance change memory includes a first memory cell, a word line, a first bit line, first and second inverters, first to sixth MOS transistors, and a control circuit. The first transistor is connected to the first output terminal of the first inverter. The second transistor is connected to the second output terminal of the second inverter. The fifth transistor has a first current path whose one end is connected to the first voltage terminal of the first inverter. The sixth transistor has a second current path whose one end is connected to the third voltage terminal of the second inverter. The control circuit makes the first and second transistors a cutoff state by a first signal and makes the fifth and sixth transistors the cutoff state by a second signal in a standby state.

According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.

According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.

Growing community of inventors

Seongnam-si, South Korea

Masahiro Takahashi