Nec Corporation

Masahiro Shigihara

Toru Takamichi

Kiyoshi Fukuchi

A phase excursion compensation circuit of a phase modulation signal demodulator detects occurrence of a slip of a received signal from a change in a phase compensation amount that is formed into the received signal by a phase excursion compensation unit, and corrects the phase compensation amount of the received signal after the slip is generated.

Phase compensation receiver

A multiplexing apparatus stores fixed length data into which information signals supplied from channels are divided; determines an output channel by selecting the each channel cyclically; acquires the fixed length data from the output channel based on a channel multiplexing ratio number to store the fixed length data in a payload in turn; adds assignment information to the payload; and creates a multiplexing frame by using the payload to transmit to a transmission channel. A demultiplexing apparatus detects the assignment information from the payload of the multiplexing frame received to the transmission channel; creates distribution information for distributing the fixed length data to each channel based on the assignment information; detects the fixed length data from the payload to distribute the fixed length data to each channel based on the distribution information; and couples the fixed length data to reproduce the information signal.

Multiplexing transmission system, multiplexing apparatus, demultiplexing apparatus and a multiplexing transmission system

A cyclic code processing circuit, network interface card, and method for calculating a remainder from input data comprising a plurality of bits arranged in parallel. The calculation is performed by first computing a first remainder obtained by dividing an integral multiple data block by a generator polynomial, the integral multiple data block comprising a plurality of words that precede the final word of the input data. Then, a second remainder is computed by dividing the final word by the generator polynomial, the final word comprising the parallel bits located at the end of the input data. The input data remainder is calculated using the first and the second previously calculated remainders.

Cyclic code processing circuit, network interface card, and cyclic code processing method

To eliminate the need for buffering in order to calculate data length information on data as an object of computation, a first exclusive-OR unitexecutes computation of exclusive-OR of a cyclic code R(x) of the integral multiple bit bits block A(x) and a data string of M bits, containing the fraction bits block B(x). A first shifting unitshifts the exclusive-OR of the cyclic code R(x) and the data string of M bits, containing the fraction bits block B(x), by {M&#x2212;H(k)} bits toward a least significant side, where M is a parallel width and H(k) is a bit length of the fraction bits block B(x). An R'(x) generation unitgenerates a cyclic code R&#x2032;(x) that is a cyclic code of the data after shifting. To obtain R&#x2033;(x), a second shifting unitshifts the cyclic code R(x) by H(k) bits toward a most significant side. A second exclusive-OR unitexecutes computation of exclusive-OR of the cyclic code R&#x2032;(x) and data R&#x2033;(x).

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Tokyo, Japan

Masahiro Shigihara