Fujitsu Corporation

Fujitsu Microelectronics Limited

Masahiro Sano

Hitoshi Watanabe

Koji Abe

Toshiaki Sugioka

Makoto Saito

Tadashi Konno

A frame input unit receives an input of a frame having a placement area for an element to which a predetermined signal is supplied. A netlist input unit receives an input of a netlist concerning the element. A placing unit places the element in the placement area of the frame input by the frame input unit based on the netlist input by the netlist input unit. A detecting unit detects whether there is a vacant position in the placement area in which the element is placed by the placing unit, and a bypass-element placing unit places a bypass element at the vacant position detected by the detecting unit, the bypass element propagating the predetermined signal by bypassing the element located adjacent to the vacant position.

Layout design apparatus, layout design method, and computer product

A method for designing an integrated circuit such as a VLSI circuit, in particular optimizing delay of a signal transmitting through signal lines connecting a signal supplying source to each of elements, whereby skew can be decreased. The method can include determining whether the signal source satisfies a fan-out restriction if the signal source supplies a signal to all of the driven elements which are directly connected to the signal source, dividing the elements into groups so that the fan-out restriction is satisfied in each of the groups and each of the groups has the same or substantially same load capacity, when the signal source does not satisfy the fan-out restriction, and inserting into each group, a buffer having a size which makes the groups of elements satisfy the fan-out restriction. The dividing and the buffer inserting are repeated until a positive determination is delivered on the fan-out restriction.

Method of optimizing signal lines within circuit, optimizing apparatus, recording medium having stored therein optimizing program, and method of designing circuit and recording medium having stored therein program for designing circuit

A method of forming a tree structure type circuit includes the steps of dividing a division target region of LSI into a plurality of regions, placing constituent elements as distribution targets in the regions, forming a tree, conducting schematic routing, and conducting timing improvement while considering a clock skew. These processings are repeated by a preset number of times. If the repetition number reaches a specified number, the constituent elements and an added buffer or the like are subjected to detailed placement, and automatic routing is conducted.

Method of forming tree structure type circuit, and computer product

There is provided a method utilized when designing an integrated circuit such as a VLSI or the like. The method is utilized for optimizing the delay of a signal transmitting through signal lines connecting a signal supplying source to each of elements, whereby skew can be positively decreased. The method includes a step (S ) of determining whether or not the signal supplying source satisfies a fan-out restriction if the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source, a step (S ) of dividing the plurality of elements into a plural number of groups so that the fan-out restriction is satisfied in each of the groups and that each of the groups has the same or substantially the same load capacity, when it is determined that the signal supplying source does not satisfy the fan-out restriction, and a step (S ) of inserting into each of the groups, a buffer element having a size which makes the groups of elements satisfy the fan-out restriction. The buffer element inserted at the buffer inserting step (S ) is regarded as a driven element and then it is again determined in the determining step (S ) whether or not the signal supplying source satisfies the fan-out restriction under the condition that the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source. The dividing step (S ) and the buffer inserting step (S ) are repeatedly carried out until positive determination is delivered on the fan-out restriction.

METHOD OF OPTIMIZING SIGNAL LINES WITHIN CIRCUIT, OPTIMIZING APPARATUS, RECORDING MEDIUM HAVING STORED THEREIN OPTIMIZING PROGRAM, AND METHOD OF DESIGNING CIRCUIT AND RECORDING MEDIUM HAVING STORED THEREIN PROGRAM FOR DESIGNING CIRCUIT

The present invention is a method that can simultaneously and reliably optimize the clock propagation delay time and clock skew of the entire semiconductor integrated circuit. For this reason, in the present invention, a clock-supplying element and a plurality of clock-receiving elements are first disposed. Then, a wiring path is determined while adjusting both a wired state and a buffer-inserting position from the clock-receiving elements toward the clock-supplying element. Such a method according to the present invention is employed, for example, in the layout of a semiconductor integrated circuit such as an integrated circuit, a large-scale integration, etc. Particularly, it is employed in the automatic layout of a clock distributing circuit.

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Kawasaki, Japan

Masahiro Sano