Matsushita Electric Industrial Co., Ltd.

Fujitsu Corporation

Masahiro Oohashi

Tsuyoshi Nakamura

Shunichi Kuromaru

Masayoshi Tojima

Yasuo Kohashi

Hiromasa Nakajima

Akira Yamamoto

Masatoshi Matsuo

Tomonori Yonezawa

Mana Hamada

Yuichiro Sakane

Toshihiro Moriiwa

Hiromu Yoshii

Hiroki Ootsuki

An optical transmitter and receiver has stored in advance therein FEC techniques and applicable conditions for applying the FEC techniques to a counterpart optical transmitter and receiver. The optical transmitter and receiver measures a state of receiving data transmitted from the counterpart optical transmitter and receiver, determines an applicable condition satisfying the measured data reception state from among the stored applicable conditions, and selects a FEC technique stored in association with the applicable condition determined as satisfying. The optical transmitter and receiver then notifies the counterpart optical transmitter and receiver of the selected FEC technique.

Optical transmitter and receiver and optical transmission and reception system

The image processing apparatus according to the present invention comprises: DMA control meanshaving image input/output processing means, an external memory, DMA setting holding means, address generating means, DRAM control means, DMA request generating means, and DMA request adjusting means; a processorincluding encoding/decoding processing means; and a DMA busas shown in FIG. In the image processing apparatus so constructed, a transfer data group which can be previously subjected to DMA scheduling is divided into burst transfer units, and the DMA request generating means periodically issues the DMA request in the burst transfer units and performs DMA of the transfer data which cannot be subjected to the DMA scheduling during the period that the DMA of the transfer data is not performed, thereby avoiding concentration of specific DMA.

Image processing device

A deblocking filter arithmetic apparatus and a deblocking filter arithmetic method employed for removing block noises generated at decoding image data which have been subjected to the encoding process. Successive pixel data are input to eight arithmetic blocks () every two data, a filtering processing arithmetic for removal of the block noises is carried out in parallel so as to conclude the filtering processing arithmetic in a unit of the combination of two arithmetic blocks in an order successively, thereby the pixel data obtained by performing the filtering processing are output by a pipeline system in a unit of the combination of the arithmetic blocks from an output selection circuit ().

Deblocking filter arithmetic apparatus and deblocking filter arithmetic method

The time required for access to a SDRAM () is extracted from the layout of an integrated circuit (), a first phase difference between an external clock SDCLKO and an internal clock ICLK is calculated, and the value of delay of the external clock signal or the internal clock signal in the integrated circuit () is changed on the basis of the calculated first phase difference, whereby clock phase adjustment for the integrated circuit () in the designing stage is realized.

Clock phase adjustment method, integrated circuit, and method for designing the integrated circuit

An image processing apparatus according to the present invention comprises a general arithmetic circuit comprising a program control circuit , a first address generator , a first data memory , a first pipeline operation circuit , a second address generator , a second data memory and a second pipeline operation circuit , and a dedicated arithmetic circuit comprising a control circuit , a first dedicated pipeline operation circuit , a second dedicated pipeline operation circuit , . . . , an N-th dedicated pipeline operation circuit , as shown in FIG. The arithmetic unit having the above-described structure, for example, can realize an arithmetic unit which can be applied to various applications. Further, considering the age of IP (Intellectual Property) which will come in the future, the arithmetic unit can exhibit the flexibility toward the applications.

Processor and image processing device

Filter arithmetic device

There is provided a DCT processor for performing at least one of DCT operation and inverse DCT operation for image data in unit blocks having different sizes. This DCT processor is provided with a bit slice circuit ( ) for outputting, bit by bit, the pixel data inputted for each column or row; a first butterfly operation circuit ( ) for subjecting the output data of the bit slice circuit ( ) to butterfly operation; a ROM address generation circuit ( ) for generating continuous ROM addresses; an RAC ( ) for reading the data corresponding to the ROM addresses from ROMs (ROM &tilde;ROM ) and accumulating the data by accumulation circuits ( ); and a second butterfly operation circuit for subjecting the output data of the RAC to butterfly operation.

Dct arithmetic device

The time required for access to a SDRAM ( ) is extracted from the layout of an integrated circuit ( ), a first phase difference between an external clock SDCLKO and an internal clock ICLK is calculated, and the value of delay of the external clock signal or the internal clock signal in the integrated circuit ( ) is changed on the basis of the calculated first phase difference, whereby clock phase adjustment for the integrated circuit ( ) in the designing stage is realized.

Growing community of inventors

Fukuoka, Japan

Masahiro Oohashi