Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Corporation of America

Masahiro Ohashi

Mana Hamada

Tsuyoshi Nakamura

Masayoshi Tojima

Masatoshi Matsuo

Yuji Sugisawa

Miki Arita

Ryuji Fuchikami

Hiroto Tomita

Tomonori Yonezawa

Shunichi Kurohmaru

Masayoshi Toujima

Yasuo Kouhashi

Takashi Yamamoto

Takashi Hashimoto

Tadanori Tezuka

Akira Motohara

Masashi Hoshino

Yoshiteru Tanaka

Miwaka Takahashi

Toshiyuki Yokoyama

Youichi Nishida

Toshihiro Moriiwa

Maiko Taruki

A histogram generator generates a histogram that indicates a count of pixels of a designated color in association with coordinates along a basic axis of a screen, for frame image data obtained by filming a real space. A histogram smoother performs smoothing of the generated histogram. A three-dimensional coordinates generator selects a value associated with particular coordinates from among the counts indicated in the smoothed histogram, and performs depth value determination for a target object using the selected value.

Image processing device, stereoscoopic device, integrated circuit, and program for determining depth of object in real space generating histogram from image obtained by filming real space and performing smoothing of histogram

A projection apparatus projects pattern light onto an object, the pattern light including pattern images corresponding to information that indicates coded projection coordinates in a projection coordinate system. Each of the pattern images includes two or more continuous areas. Widths of the two or more continuous areas are identical to one another, while lengths of the two or more continuous areas are different. An imaging apparatus captures images created on the object and generates captured images including imaging pixel values at imaging pixel coordinates in an imaging coordinate system. An image correction apparatus generates, based on the captured images, coordinate conversion information that associates the projection coordinates with the imaging pixel coordinates and corrects a projection image by using the coordinate conversion information.

Projection system, semiconductor integrated circuit, and image correction method

A projection system includes a projection apparatus that projects, onto an object, pattern light indicating pattern images obtained by conversion of projection coordinates defined in a projection coordinate system to codes, an imaging apparatus that captures images created on the object by projecting the pattern light onto the object and that generates first captured images, and an image correction apparatus that generates, based on the first captured images, first coordinate conversion information which associates the projection coordinates with imaging pixel coordinates defined in an imaging coordinate system of the imaging apparatus and that corrects a projection image, which is prepared in advance, by using the first coordinate conversion information.

A variable length decoding device comprises a CPU, a variable length decoding unit, an encoded data memory, a decoded data memory, and a mass memory. The variable length decoding unit comprises a decoding table memory operable to store decoding table, a standard information storage unit operable to store standard information of encoded data, and a frequency information storage unit operable to store information on frequency of usage of each table element of the decoding table. According to the structure, the decoding table is not necessary to transfer when decoding the encoded data based on the same standard of the previously-decoded encoded data. The decoding table to be stored in the decoding table memory can be composed by table elements of higher frequency of usage, thereby decreasing occurrence of cache error.

Variable length decoding method and device

A data processing apparatus comprises a plurality of calculating units connected each other in series, a plurality of memories connected in between the plurality of calculating units, and a control unit operable to determine a calculating unit, which performs calculation in a unit cycle, among the plurality of the calculating units. It is possible to reduce unnecessary power consumption in the data processing apparatus while completing processing in permissible processing time set by an application.

Data processing apparatus

Portable terminal equipment includes an upper chassis, a lower chassis, a connector therebetween, a camera holder, and a camera. The upper chassis includes the first obverse side and the first reverse side. The lower chassis includes the second obverse side and the second reverse side. The connector is operable to collapsibly interconnect the upper and lower chassis. The camera holder is slidable outward and inward with respect to either the upper chassis or the lower chassis. The camera is disposed on the camera holder in a relationship coextensive with the first obverse side. When the upper and lower chassis are opened up, then images taken by the camera are displayed on a first display. When the upper and lower chassis are folded up, then images taken by the camera are displayed on a second display. Thus the thinned portable terminal equipment including the single camera is operable to photograph both a user and any other subject.

Portable terminal equipment

Image data is separated from three lines of image data in accordance with a storage capacity of a source memory. The separated image data is transferred to the source memory, Several pieces of image data are read out in sequence from the transferred image data and forwarded to a filtering process. These operations are then repeated to provide a line of filtered image data.

Image-processing method and image processor

In a four-by-four orthogonal transform mode, an input data buffer enters a first half of entered eight pieces of pixel data, i.e., 'x0A', 'x1A', &#x201c;x2A&#x201d;, and &#x201c;x3A&#x201d;, into each of the first to fourth multiply-and-accumulation (MAC) operation circuits, while feeding a second half of the entered eight pieces of pixel data, i.e., &#x201c;x0B&#x201d;, &#x201c;x1B&#x201d;, &#x201c;x2B&#x201d;, and &#x201c;x3B&#x201d;, into each of the fifth to eighth MAC operation circuits. In an eight-by-eight orthogonal transform mode, the input data buffer feeds entered eight pieces of pixel data into each of the first to eighth MAC operation circuits. Since the input data buffer receives the eight pieces of pixel data in each of the four-by-four and eight-by-eight orthogonal transform modes, an orthogonal transform circuit is activated once in each of the four-by-four and eight-by-eight orthogonal transform modes. In both of the four-by-four and eight-by-eight orthogonal transform modes, the same first to eighth MAC operation circuits are used to produce the orthogonal transform coefficient data. This feature inhibits an increase in hardware area.

Orthogonal transform method and apparatus

An image processing unit decodes coded data that have been coded and synthesizes the decoded moving image with graphics data. In a case where only graphics data are to be displayed, a bypass unit outputs the graphics data to a display device without use of an image processing unit. A control unit performs control of the supplying of a power supply voltage and a clock to a region containing the image processing unit and performs control of the bypass unit. If processing at the image processing unit is unnecessary, the supply of a power supply voltage or the supply of a clock to the region containing the image processing unit is stopped so as to stop the region and enable reduction of wasteful power consumption.

Data processing system for reducing wasteful power consumption

A system which allows signal transmission between circuit blocks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.

Method of designing semiconductor integrated circuit device

The method for designing an integrated circuit device of the present invention includes the steps of: obtaining the number of operations by a functional simulation; determining a specification model based on the number of operations; determining an behavioral model corresponding to the specification model based on the number of operations per cycle required; determining a RTL model corresponding to the behavioral model based on the number of operations per cycle required; and obtaining design data corresponding to the RTL model for implementing the function.

Method of designing integrated circuit device using common parameter at different design levels, and database thereof

A system which allows signal transmission between circuit locks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.

A variable length coding (VLC) method and a variable length coding apparatus for producing variable length coding having a reduced number of arithmetic cycles. The method includes carrying out (a) performing a VLC process and assigning a code to a combination of (Last, Run, Level), (b) subtracting LMAX as the maximum Level corresponding to (Last, Run) from Level to calculate amended Level and thereafter assigning a code to a combination of (Last, Run, amended Level), (c) subtracting a value that is obtained by adding 1 and RMAX as the maximum Run corresponding to (Last, Level) from Run to calculate amended Run and thereafter assigning a code to a combination of (Last, amended Run, Level), and (d) of performing faxed length coding (FLC) assignment in parallel with each other, and includes (e) selecting the code according to predetermined priorities.

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Fukuoka, Japan

Masahiro Ohashi