Denso Corporation

Masahiro Ogino

Yukihiro Kato

Masakiyo Sumitomo

Yutaka Tomatsu

Yoshihiko Isobe

Hidetoshi Muramoto

Seigo Oosawa

Hisayoshi Ooshima

Tomomi Oobayashi

A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer and a carrier storage layer over the drift layer; a collector layer on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and the carrier storage layer and reaching the drift layer; a gate electrode on an insulation film in each trench; and an emitter region in a surface portion of the base layer contacting each trench. A thickness of at least a portion of a part of the gate insulation film on a sidewall of each trench on a collector layer side from a peak position, at which the impurity concentration of the carrier storage layer is highest, is thicker than a thickness of another part of the gate insulation film on the sidewall of an opening portion side of the trench from the peak position.

Semiconductor device

In a semiconductor device, a first conductivity-type first semiconductor region that abuts on a side surface of a contact trench adjacent to an opening portion of the contact trench, and has a higher impurity concentration than that of a second semiconductor layer is formed. Also, a second conductivity-type second semiconductor region that abuts on a bottom surface of the contact trench and a side surface of the contact trench adjacent to the bottom surface of the contact trench, and has a higher impurity concentration than that of a first semiconductor layer is formed. A first electrode that is connected electrically with the first semiconductor region and the second semiconductor region is disposed in the contact trench. Even when the semiconductor device is miniaturized by reducing the width of the contact trench, a breakage of the semiconductor device when switched from an on-state to an off-state is reduced.

Semiconductor device and method for manufacturing the same

An MIS transistor fabricated in a manner that minimizes the occurrence of leak currents and that improves overall transistor performance by minimizing variation in location of the transistor source and drain during fabrication thereof. A gate electrode is first fabricated on a substrate. Next, a thermal oxide layer is formed on a side of the gate electrode. A masking process is then performed with the thermal oxide layer to form a source and a drain. A silicon oxide layer is then deposited over the gate electrode, the source and the drain. An etching process is performed on the silicon oxide to form a side wall oxide film over the thermal oxide layer on the side of the gate electrode and to expose surfaces of the gate electrode, the source and the drain. A metal film is then deposited over the gate electrode, the source and the drain and is heat treated to form a metal silicide film on the exposed surfaces of the gate electrode, the source and the drain. The side wall oxide film functions to disperse the metal silicide film as it is deposited to electrically separate the gate electrode, the source and the drain, thereby preventing a leakage current from occurring.

Insulated gate transistor with leakage current prevention feature

Growing community of inventors

Kariya, Japan

Masahiro Ogino