Fujitsu Corporation

Spansion Llc.

Fujitsu Vlsi Limited

Masahiro Niimi

Takaaki Furuyama

Mitsuhiro Nagao

Yoshihiro Takemae

Yasuharu Satoh

Shinya Fujioka

Yasuharu Sato

Tadao Aikawa

Kenta Kato

Koji Shimbayashi

Makoto Niimi

Yukihiro Nomura

Hiroyuki Kobayashi

Hitoshi Ikeda

Kenji Nagai

Katsuhiro Mori

Takashi Miyamoto

Toshio Komasaka

Ichizou Mikami

Masahiko Yano

Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks Bto Bin a sector, in which a block address BA for selecting one of blocks Bto Bis held in block address buffer (BAB). Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB)is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption.

Storage device, control method of storage device, and control method of storage control device

A communication apparatus for receiving maintenance data required for maintaining a device to be maintained and supplying maintenance data to the device to be maintained, and method are provided. The communication apparatus includes an acquisition unit for acquiring identification information for identifying the device and a sending unit for sending identification information acquired by the acquisition unit. The apparatus includes a receiving unit for receiving maintenance data including the identification information sent by the sending unit and a supply unit for supplying said maintenance data received by said receiving unit to said device to be maintained.

Communication apparatus, maintenance system, maintenance method and computer program

A nonvolatile memory devicecapable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory deviceis provided with a plurality of banks, a rewrite control unitto which a first power source line VCCand a first ground line VSSare connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unitto which a second power source line VCCand a second ground line VSSare connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unitand the read control unitare arranged so as to be spaced from each another.

Nonvolatile memory device having a plurality of memory blocks

A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.

Memory employing independent dynamic reference areas

A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

Memory employing separate dynamic reference areas

A nonvolatile storage including a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.

Nonvolatile storage and erase control

Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

Fuse circuit

A semiconductor memory device that performs a flash write operation without increasing the circuit area. Column selection lines CL -CL extend parallel to word lines at locations corresponding to where column gates are formed. During a flash write mode, the subcolumn decoder simultaneously selects the column selection lines. This writes cell information to every memory cell connected to the selected word line.

Method for writing data to semiconductor memory and semiconductor memory

According to an aspect of the present invention, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area. According to the present invention, there is provided a memory device having a plurality of banks each including a plurality of memory cells, and reading or writing data from or into the memory cells in synchronism with a clock signal, the memory device comprising: a sense amplifier disposed on each of the plurality of banks, for amplifying data read from the memory cells; a plurality of common data buses shared by the plurality of banks, the number of the common data buses being less than the number of the banks; and a switching circuit disposed on each of the plurality of banks, for feeding or receiving data of the each bank to or from the plurality of common data buses; wherein read or write of data of the plurality of banks is made through successive selection of the plurality of common data buses by the switching circuit.

Memory device with a plurality of common data buses

A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

DRAM with reduced electric power consumption

A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Each client unit 2 diagnoses its operation environment (hardware, software, firmware and so on) at the start time of itself, and when an abnormality or any change (deletion, modification or creation) has occurred and it is repairable, the client unit 2 itself repairs itself or maintenance process is conducted by reinstallation from the server unit 1. When it is unrepairable, the client unit 2 releases itself from the LAN line 100. In this way, by having the client unit 2 be provided with self maintenance capability to allow each client unit 2 to conduct the self maintenance of itself such a client/server system is realized by which loads of the server unit 1 and the LAN line 100 are reduced as well as the probability of system down occurrence is lowered, further the capability of the entire system is improved and a maintenance engineer or a user is not required much labor.

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Okazaki, Japan

Masahiro Niimi