Matsushita Electric Industrial Co., Ltd.

Masahiro Nakatani

Takehiro Hirai

Mitsuo Tanaka

Akihiro Kanda

A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

Semiconductor Bi-MIS device

Method of manufacturing Bi-MOS device

A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar transistor, a polysilicon film as a conductive film is laid on the entire substrate and selectively etched to form electrodes. In a MIS transistor, the protection film of the silicon nitride film serves as a gate insulator film and the protection film of the polysilicon film serves as a gate electrode. Accordingly, contamination to the gate insulator film at formation of contact holes of the bipolar transistor is prevented, and an excellent semiconductor with Bi-MOS structure is manufactured with low cost.

Semiconductor Bi-MIS device and method of manufacturing the same

The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

Semiconductor device including IIL and vertical transistors

In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.- -type diffused layer 12 serving as the base thereof are respectively so formed as to be adjoining to the oxide film 101 of the emitter lead-out portion of the IIL; and a p-type diffused layer 16 serving as the base of the vertical npn transistor is so formed as to be adjoining to the oxide film 101 of the collecter wall. The semiconductor device can achieve a smaller cell size, a decrease in parasitic capacitance and an increase in operating speed.

Semiconductor device including integrated injection logic and vertical

The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.

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Osaka, Japan

Masahiro Nakatani