Fujitsu Corporation

Masahiro Mishima

Akira Watanabe

Go Sugizaki

Shigekatsu Sagi

An apparatus includes a processor, first and second request-controllers, and a buffer. The processor divides a data-transfer request into transfer-requests including first and second transfer-requests. When, within a memory, an end-address of readout data based on the first transfer-request is adjacent to a head-address of readout data based on the second transfer-request, the processor sets end-adjacency information in the first transfer-request and sets head-adjacency information in the second transfer-request. Then, the first request-controller sets first adjacency information in a first readout-request for a readout end-address of the first transfer-request. The second request-controller sets second adjacency information in a second readout-request for a readout head-address of the second transfer-request. In response to the first readout-request, the buffer retains data read out from the memory, and outputs the data to the first request-controller. In response to the second readout-request, the buffer outputs the retained data to the second request-controller.

Data transfer device, arithmetic processing device, and data transfer method

A data transfer circuit includes a write circuit to control writing of write data to a memory, a read circuit to control reading of data from the memory, a first circuit to register a store position in the memory at which data written to the memory is stored, and a second circuit to store a data pattern when the write data is comprised of repeated patterns each identical to the data pattern, wherein the write circuit does not register the store position in the first circuit with respect to the written data that is comprised of the repeated patterns each identical to the data pattern stored in the second circuit, and the read circuit reads the data pattern from the second circuit for provision to a source issuing a read request when data requested by the read request corresponds to the data pattern stored in the second circuit.

Data transfer circuit and data transfer method

A request processing device includes a request sender that sends a write request or a read request to a storage device, a response processor that receives a response to a request which the request sender has sent, and a test request processor that converts a read response which is a response to a read request, into a test write request, and converts a write response which is a response to a write request into a test read request, from among responses that the response processor has received or from among responses that have been input from a device which is provided outside the request processing device.

Request processing device, request processing system, and access testing method

A system module includes a plurality of processors, and a system controller that is connected to the processors via a first transmission line and relays a packet from each of the processors to another system module via a second transmission line in a multiprocessor system. The system controller includes a data transmission controller that, when part of packets constituting a series of data is not received normally from a processor due to a fault in the processor or the first transmission line, generates a supplement packet for a packet that has not been received normally and outputs the supplement packet to the second transmission line.

System module and data relay method

A system controller is presented that controls an output format of data according to a data congestion status of the data and then outputs the data over an output bus. Specifically, if there is data congestion, the system controller changes the format of the data to a format that matches a bus width of the output bus before outputting the data over the output bus. To give a specific example, the system controller changes the format of the data input over an input bus in an input format of 4 B to an output format of 5 B before outputting the data over the output bus. If there is no data congestion, the system controller outputs the data over the output bus without changing the input format.

Data input-output control apparatus

A system controller, which executes a speculative fetch from a memory before determining whether data requested for a memory fetch request is in a cache by searching tag information of the cache, includes a consumption determining unit that monitors a consumption status of a hardware resource used in the speculative fetch, and determines whether a consumption of the hardware resource exceeds a predetermined value; and a speculative-fetch issuing unit that stops issuing the speculative fetch when the consumption determining unit determines that the consumption of the hardware resource exceeds the predetermined value.

System controller, speculative fetching method, and information processing apparatus

After packets received by receiving latches have been divided into individual words and the words have been stored into buffer queues, the packets read from the buffer queues are stored into packet storage queues. A format determining circuit has defined in advance a plurality of types of writing formats and, when a packet is received by any of the receiving latches, determines dynamically a writing format according to availability of the buffer queues at this time. Then, a packet control circuit divides the received packets into individual words and stores the words into the buffer queues, according to the determined writing format.

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Kawasaki, Japan

Masahiro Mishima