Hitachi, Ltd.

Renesas Electronics Corporation

Masahiro Masunaga

Akio Shima

Ryo Kuwana

Shintaroh Sato

Takayuki Hashimoto

Isao Hara

Mutsuhiro Mori

Digh Hisamoto

Mutsumi Suzuki

Shinji Nomoto

Provided is a SiC semiconductor element equipped with a SiC integrated circuit having a stable characteristic, which operates normally even in a radiation environment. A radiation resistant circuit device includes: a SiC semiconductor element equipped with a SiC integrated circuit, a printed board on which the SiC semiconductor element is provided, a conductive wiring that is arranged inside the printed board and has a predetermined surface facing a bottom surface of a substrate electrode of the SiC integrated circuit, and an insulating material arranged between the bottom surface of the substrate electrode of the SiC integrated circuit and the predetermined surface of the conductive wiring.

Radiation resistant circuit device, pressure transmission device, and nuclear power plant measurement system

A semiconductor device includes an electrostatic protection circuitand a MOSFETincluding a gate terminal. The electrostatic protection circuitincludes a positive-side power supply terminal, a negative-side power supply terminal, a first protection diode, a second protection diode, a resistance element, and a bipolar transistor. The second protection diodeincludes an anode terminal electrically connected to the negative-side power supply terminalvia the resistance element, and a cathode terminal electrically connected to the gate terminal. The bipolar transistorincludes a base terminal, an emitter terminal, and a collector terminal. The bipolar transistoris electrically connected to the anode terminal of the second protection diode, the gate terminal, and the positive-side power supply terminal. The electrostatic protection circuitis formed on a semiconductor substrate made of silicon carbide.

Semiconductor device

The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.

Semiconductor device, method of manufacturing same, and sensor

An n type semiconductor layer is formed over an n type semiconductor substrate made of silicon carbide, a p type impurity region is formed in the semiconductor layer, and an n type drain region and an n type source region are formed in the impurity region. A field insulating film having an opening that selectively opens a part of the impurity region located between the drain and source regions is formed over the impurity region and the drain and source regions. A gate insulating film is formed over the impurity region in the opening, and a gate electrode is formed on the gate insulating film. Here, a field relaxation layer having an impurity concentration higher than that of the impurity region is formed in at least a part of the impurity region located between the drain and source regions in plan view and located below the field insulating film.

Semiconductor device, manufacturing method thereof, and pressure transmitter using semiconductor device

A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.

Semiconductor device and method of manufacturing the same

There is provided a semiconductor device that improves reliability. The impurity concentrations of a psource region and a pdrain region are 5&#xd7;10cmor more. The channel-region-side end portion of a first insulating film is disposed on a psource region. The end portion has an inclined surface where the first insulating film thickness is reduced from the psource region toward a channel region. The channel-region-side end portion of a second insulating film is disposed on a pdrain region. The end portion has an inclined surface where the second insulating film thickness is reduced from the pdrain region toward the channel region. A gate electrode is disposed on the channel region, the psource region, the pdrain region, and the inclined surfaces of the first and the second insulating films through a gate insulating film including an aluminum oxide film.

Semiconductor device and method of manufacturing semiconductor device

The present invention provides a switching device () for power conversion in which a first gate electrode (), a p-type channel layer () having an n-type emitter region (), a second gate electrode (), and a p-type floating layer () are repeatedly arranged in order on the surface side of an n-type semiconductor substrate (). An interval a between the two gates () that sandwich the p-type channel layer () is configured to be smaller than an interval b between the two gates () that sandwich the p-type floating layer (). The first gate electrode () and the second gate electrode () are both supplied with drive signals having a time difference in drive timing.

Switching device for power conversion and power conversion device

There is provided a semiconductor device including a first emitter layer of a first conductivity type, a drift layer of a second conductivity type, adjacent to the first emitter layer, a channel layer of the first conductivity type, adjacent to the drift layer, a second emitter layer of the second conductivity type, adjacent to the channel layer, a collector electrode electrically coupled to the first emitter layer, an emitter electrode electrically coupled to the second emitter layer, a first trench-gate electrode for controlling on and off of an electric current flowing between the collector electrode and the emitter electrode, and a second trench-gate electrode for controlling a turn-off power loss. The semiconductor device further includes a thyristor unit made up of the first emitter layer, the drift layer, the channel layer, and the second emitter layer. Further, the electric current has saturation characteristics in a short circuit state, and short circuit capability of a double-gate semiconductor switching device is improved because the magnitude of electric current flowing during a short circuit is under control due to the electric current saturation characteristics.

Semiconductor device and electric power converter in which same is used

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

Growing community of inventors

Tokyo, Japan

Masahiro Masunaga