Fujitsu Corporation

Masahiro Kuramoto

Jun Tsuiki

Junichi Inagaki

Masao Koyabu

Shuji Yamamura

Takumi Maruyama

Masato Nakagawa

Junji Ichimiya

Makoto Komagata

A processor includes: an address generating unit that, when an instruction decoded by a decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets; a plurality of instruction queues that hold the generated address sets corresponding to the respective operand sets, in correspondence to respective processing units; and a plurality of processing units that perform the arithmetic processing in parallel on the operand sets obtained based on the respective address sets outputted by the plurality of instruction queues.

Processor and control method of processor for address generating and address displacement

An arithmetic processing device includes, a memory that stores a first data and a second data, a plurality of arithmetic circuits, a first memory arranged for each of the arithmetic circuits and that stores a first predetermined row having the predetermined number of the first data stored in the memory, a second memory arranged for each of the arithmetic circuits and that stores a second predetermined row having a predetermined number of the second data stored in the memory, and a plurality of multiply-add arithmetic circuits arranged for each of the arithmetic circuits, a number of the multiply-add arithmetic circuits corresponding to the predetermined number, each of the multiply-add arithmetic circuits that obtains a third data by executing the operation using the first data and the second data based on a result of performing a row operation which is an operation of one row of the first data.

Arithmetic processing device and control method for arithmetic processing device

Each of product-sum arithmetic unitstoacquires, from a register file, different pieces of first element data included in a first predetermined row of first data that forms a matrix; acquires, from a register file, same pieces of second element data included in a second predetermined row of second data that forms a matrix; performs a row portion operation that is an operation performed on the first data by an amount corresponding to a single row by performing a process of performing an operation using the acquired first element data and the second element data; and performs an operation by using the first data and the second data based on the result of the row portion operation.

Arithmetic processing device and control method of the arithmetic processing device

A memorystores therein first data and second data each of which has element data that forms a matrix. Arithmetic unitstorepeat, for each of a first predetermined row of the first data and a second predetermined row of the second data that are stored in the memory, by using the element data included in the first predetermined row and the element data included in the second predetermined row, a row portion operation based on the number of columns in the second data and performs, by using results of the row portion operations, an arithmetic operation process that acquires the operation results of the operation that uses the first data and the second data.

Arithmetic processing device for deep learning and control method of the arithmetic processing device for deep learning

An arithmetic processing apparatus, includes: an arithmetic operation execution circuit configured to execute an arithmetic operation; a first register configured to store data to be used for an arithmetic operation by the arithmetic operation execution circuit; a first buffer configured to store data; a first controller configured to store, when an array of data is changed and the changed data is stored into the first register as the data to be used for the arithmetic operation, a plurality of data groups, which are successively received, into the first buffer; and a second controller configured to successively output, every time each of the plurality of data groups is stored into the first buffer, data included in the data groups stored in the first buffer to the first register.

Arithmetic processing apparatus and control method for arithmetic processing apparatus

A plurality of floating-point registers store data therein. A processing execution unit executes arithmetic processing by using data stored in the floating-point registers. A first switch and a second switch select a route connecting the processing execution unit and the floating-point registers. A switch control unit controls the first switch and the second switch so as to switch a route to be selected, based on a switching instruction from the processing execution unit.

The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead. The asynchronous transmission device that receives at least one notification signal in accordance with a reception clock, the notification signal being transmitted in accordance with a transmission clock, includes a trigger signal transmission unit that outputs a trigger signal which is based on the symbol period of the notification signal, a notification signal transmission unit that outputs a notification signal which has its timing staggered by a predetermined time period with respect to the timing of the trigger signal output from the trigger signal transmission unit, a trigger signal synchronization unit that synchronizes the trigger signal, and outputs a sampling timing signal which indicates the sampling timing of the notification signal, and a notification signal retention unit that retains the notification signal in accordance with the sampling timing.

Asynchronous transmission device, asynchronous transmission method

A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.

Storage control circuit, and method for address error check in the storage control circuit

A memory device stores entries waiting to be processed. Row numbers of matrix information correspond to storage positions within the memory device, column numbers correspond to positions within the order of the entries, and every matrix element corresponding to the storage position and the position within the order of the entry stored in this storage position has a predetermined value. An operation between the first vector information indicating storage positions of processable entries and each column of the matrix information is performed and the second vector information indicating positions within the order of the processable entries is generated. Then, a position to be processed is selected from among the positions of processable entries indicated by the second vector information, an element having the predetermined value in the column corresponding to the selected position is obtained, and an entry in the storage position corresponding to the element is processed.

Orderly processing ready entries from non-sequentially stored entries using arrival order matrix reordered upon removal of processed entries

The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.

Growing community of inventors

Kawasaki, Japan

Masahiro Kuramoto