Fujitsu Corporation

Socionext Inc.

Masahiro Kudo

Hiroshi Yamazaki

Kunihiko Gotoh

Kazuaki Oishi

Masato Yoshioka

Tomoyuki Arai

Daisuke Suzuki

Hiroyuki Nakamoto

Shinji Yamaura

Nobuhiko Kobayashi

Kotaro Murakami

An amplifier circuit includes: an input circuit configured to receive an input signal; a load circuit provided in series with the input circuit and including a first variable resistance unit and a second variable resistance unit, a resistance value of the first variable resistance unit being controlled by a digital code, a resistance value of the second variable resistance unit being controlled by an analog control voltage; and a correction circuit including a third variable resistance unit having a circuit configuration corresponding to the first variable resistance unit and a fourth variable resistance unit having a circuit configuration corresponding to the second resistance unit, a resistance value of the third variable resistance unit being controlled by the digital code, a resistance value of the fourth variable resistance unit being controlled by the analog control voltage, the correction circuit being configured correct a resistance value of the load circuit.

Amplifier circuit, reception circuit, and semiconductor integrated circuit

An equalizer circuit includes: an addition circuit configured to add an input signal and a compensation signal; a comparison circuit configured to compare an output signal of the addition circuit; a plurality of first latch circuits configured to hold an output signal of the comparison circuit, the plurality of first latch circuits being connected in cascade; a selection circuit configured to select and output one of output signals of the comparison circuit and the plurality of first latch circuits; a second latch circuit configured to hold an output signal of the selection circuit; and a digital analog conversion circuit configured to generate the compensation signal, based on an output signal of the second latch circuit.

Equalizer circuit, reception circuit, and semiconductor integrated circuit

An equalizer circuit includes a first adder circuit adding an input signal and including an addition terminal and a subtraction terminal; a comparator circuit comparing an output signal of the first adder circuit; a latch circuit latching data output from the comparator circuit; a first digital/analog converter circuit which outputs a first signal corresponding to an absolute value of an equalizing coefficient, when the equalizing coefficient is a positive value; a second digital/analog converter circuit which outputs a second signal corresponding to an absolute value of the equalizing coefficient, when the equalizing coefficient is a negative value; and a switch circuit which switches a connection between a set of an output terminal of the first digital/analog converter circuit, an output terminal of the second digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit.

Equalizer circuit, receiver circuit, and integrated circuit device

A reception circuit includes a determination circuit including comparator circuits configured to determinate a level of a received signal and a logic circuit configured to generate a digital signal based on outputs of the comparator circuits. The determination circuit is configured to determinate by a first number of the comparator circuits when the received signal is a first signal which is a multi-valued signal and determinate by a second number of the comparator circuits, the second number being smaller than the first number, when the received signal is a second signal. The logic circuit is configured to operate as a decoder which decodes outputs of the comparator circuits and generates the digital signal when the received signal is the first signal, and operates as a selector which selects an output of the comparator circuit for generating the digital signal when the received signal is the second signal.

Reception circuit and semiconductor integrated circuit

A receiver circuit includes: a plurality of first holding circuits respectively latching a plurality of reception data pieces on the basis of a same clock signal; a comparison circuit respectively comparing first reception data pieces and second reception data pieces after a certain time elapses since the latch of the plurality of first holding circuits, the first reception date pieces being respectively latched by the plurality of first holding circuits, the second reception data pieces being respectively input to the plurality of first holding circuits; and a plurality of second holding circuits respectively latching the first reception data pieces when a first output signal of the comparison circuit indicates that the first reception data pieces and the second reception data pieces are identical.

Receiver circuit and semiconductor integrated circuit

A first P-channel transistor to a gate of which a first input signal is inputted and a second P-channel transistor to a gate of which a selection signal is inputted are provided in series between a power supply line and an output node. A first N-channel transistor to a gate of which a second input signal is inputted and a second N-channel transistor to a gate of which the selection signal is inputted are provided in series between a ground line and the output node. A third P-channel transistor to a gate of which the second input signal is inputted is provided between the gate of the second P-channel transistor and the output node, and a third N-channel transistor to a gate of which the first input signal is inputted is provided between the gate of the second N-channel transistor and the output node.

Selector circuit, equalizer circuit, and semiconductor integrated circuit

A signal generation circuit includes a limiter and a mixer. The limiter receives an input signal, allows the input signal to be off a scale at a limit voltage, and generates a phase signal indicating a phase component of the input signal. The mixer receives the input signal and the phase signal, and generates an amplitude signal indicating an amplitude component of the input signal.

Signal generation circuit

An amplifier circuit includes an amplifier unit and a current control circuit as means for achieving the aforementioned object. The amplifier unit includes a gain compensation MOS transistor compensating for gain of an output characteristic and a linearity compensation MOS transistor compensating for linearity of an output characteristic. A source of the gain compensation MOS transistor is connected to a drain of the linearity compensation MOS transistor. An input signal is applied to a gate of the linearity compensation MOS transistor. A drain of the gain compensation MOS transistor is set as an output. The current control circuit performs control so as to pass predetermined current between the drain and the source of the gain compensation MOS transistor and pass predetermined current between the drain and the source of the linearity compensation MOS transistor.

Amplifier circuit

A signal processing apparatus includes a first filter on an in-phase signal channel; a second filter on a quadrature signal channel; a plurality of filter stages having each of more than one signal paths crossing each other which connects the first filter and the second filter; and at least more than one of the filter stages of more than one of a plurality of the filter stages includes a switching circuit disconnecting more than one of the signal paths and a correction unit correcting direct current offsets of the first filter and the second filter by using the switching circuit.

Signal processing apparatus and the correcting method

In a cascode current-mirror circuit which reproduces a reference current generated by a current source and outputs the reproduced reference current: the control electrodes of first and second transistors are connected; a third transistor is cascode-connected to the first transistor through a current electrode; a fourth transistor is cascode-connected to the second transistor; the control electrodes of the third and fourth transistors are connected; the control electrode of a fifth transistor is connected to the control electrode of the first transistor and another current electrode of the third transistor, and is to be connected to the current source; and a bias-voltage generation circuit generates bias voltages for the third and fourth transistors on the basis of voltages of the control electrodes of the first and the fifth transistors.

Current-mirror circuit

A bias circuit for applying a bias voltage to a nonlinear amplification circuit, including a constant-current source; and a first, second, third, and fourth transistors, wherein a current mirror circuit is configured by the first transistor and the second transistor, and the bias voltage is outputted from the drain of the second transistor, gate lengths and gate widths of the first and second transistor are the same, gate lengths of the first to fourth transistor are the same, and gate lengths and gate widths of the first, second, third, and fourth transistor are configured so that k&#x2212;kis approximately 1, where kstands for a ratio of a gate width of the third transistor to the gate width of the first transistor and kstands for a ratio of a gate width of the fourth transistor to the gate width of the first transistor.

Bias circuit and control method for bias circuit

A control circuit Ucomprises four PMOS transistors MP-MPand receives a voltage Vn and a voltage Vss. MPand MP, and, MPand MPare respectively connected in series between power supply Vdd and a fixed voltage Vss. Gate terminal of MPis connected to Vss. Reference current and its copy current Frespectively flow through NMOS transistors Mand M, of which respective source terminals are connected to Vss. Gate width of Mis a quarter of that of M. Drain terminal is connected to the gate terminals of MPand MP. Node between source terminal of MPand drain terminal of MPis connected to gate terminal of MP, and node between source terminal of MPand drain terminal of MPis connected to gate terminal of MP. The control circuit Ucontrols gate terminal voltage of Mto make an overdrive voltage of Mbecomes Vn.

Bias circuit

A differential current mirror circuit includes: a first branching unit that branches current through a first current input terminal to a first current path and a second current path; a second branching unit that branches current through a second current input terminal to a third current path and a fourth current path; and a current mirror that copies current. The current copied by the current mirror is a combination of the current flowing through the second current path and the fourth current path and removal of the in-phase component from current through the first current path enables only the differential component flowing through the first current path to flow to a first current output terminal. Similarly, the in-phase component from current through the third current path is removed, enabling only the differential component flowing through the third current path to flow to a second current output terminal.

Differential current mirror circuit

A semiconductor circuit including a bias circuit () generating a signal reflecting a current driving capability of a transistor; an analog/digital converter circuit () converting the signal from an analog format into a digital format; and a signal processing circuit () partially controlled in an operating state or a non-operating state according to the signal converted by the analog/digital converter circuit as a control signal, is provided.

Semiconductor circuit and controlling method thereof

The first and second time-domain signals are received, and a difference between the pulse width of the first time-domain signal and the pulse width of the second time-domain signal within a unit time for carrying one item of analog signal information is obtained. The obtained difference is treated as positive information if the pulse width of the first time-domain signal is greater than the pulse width of the second time-domain signal, or as negative information if the pulse width of the first time-domain signal is smaller than the pulse width of the second time-domain signal.

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Kawasaki, Japan

Masahiro Kudo