Other

Masahiro Konnda

Tadahiro Ohmi

Tadashi Shibata

Takahisa Nitta

Akira Nakada

A semiconductor arithmetic circuit including 2 MOS (Metal Oxide Semiconductor) type transistors, the source electrodes of which are connected to one another and having gate electrodes connected to a signal line having a predetermined potential via switching elements, and having at least two input electrodes capacitively coupled with the gate electrodes, wherein a first voltage and second voltage are applied to, respectively, a first and second input electrode of a first MOS transistor. An input signal voltage is applied to both a first and second input electrode of a second MOS transistor, and then a second switching element is caused to conduct, and the gate electrodes are set to the signal line potential, then the second switching element is isolated and the gate electrodes are placed in an electrically floating state. The first voltage and the second voltage are inputted into, respectively, the first and second input electrodes of the second MOS type transistor, and the input signal voltage is inputted into the first and second input electrodes of the first MOS transistor, and thereby, the absolute value of the difference between a voltage determined in accordance with the first voltage and the second voltage and a coupling capacity ratio between the first and the second input electrodes with respect to the gate electrode, and a voltage determined by the input signal voltage and the coupling capacity ratio is calculated.

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Miyagi-ken, Japan

Masahiro Konnda