Kawasaki Steel Corporation

Kawasaki Microelectronics, Inc.

Megachips Corporation

Masahiro Konishi

Masato Yoneda

Hiroshi Sasama

Yoshinori Nishi

Yuki Narita

Naoki Kanazawa

Yoshihiro Ishida

Ryuichi Hata

Keiichi Kawana

Tomoo Tsuda

Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data.

Method and apparatus for receiving burst data without using external detection signal

A CAM (content addressable memory) device capable of flexibly coping with a wide range of user requirements with respect to operation speed and/or power consumption has operation mode setting means, generates a higher or lower internal voltage than an external power-supply voltage depending on the setting, and at least part of the internal circuit is operated by the internal voltage. In particular, the high level of the search-bit line and/or the high level of the match line are preferably set to the internal voltage. Also, the CAM device has bit line amplitude adjusting means for adjusting the amplitude of the bit line depending on the setting of the operation mode setting means and/or match line amplitude adjusting means for adjusting the amplitude of match line on which a search result is output, and thus is capable of appropriately changing the operation speed and power consumption depending on the setting.

Content addressable memory device having an operation mode setting means

The invention provides a content addressable memory device having the capability of functioning as a content addressable memory device with a reduced memory capacity even when the device includes a large number of failed words in some memory blocks. To achieve the above object, the content addressable memory device according to the present invention includes a memory part including a plurality of memory blocks which can be controlled independently of each other, a failed memory block information memory for, when there is a failed memory block, storing address information associated with the failed memory block and outputting a signal indicating the failed memory block, and an encoder for, in accordance with the signal and an address input from the outside, outputting a memory block selection signal to the respective memory blocks to enable a memory block other than the failed memory block without enabling the failed memory block.

Content addressable memory device capable of reducing memory capacity

In a binary search, two storage units are prepared so that when the least significant bit of the search address is &ldquo;0&rdquo; and &ldquo;1&rdquo;, even and odd address banks respectively are used. The search object data is classified according to data belonging to the odd and even addresses in continuous addresses and allocated to these two storage units. Further, a search tree of the search address is constructed so that two data of object for a next search are stored in different storage units. Upon the binary search, addresses for the two storage units are set according to this search tree. Therefore, simultaneous readout of data is enabled, so that readout and comparison are carried out in parallel. Further, according to multiple division search of the invention, if 2 bits of the least significant bits of the search address are &ldquo;00&rdquo;, &ldquo;01&rdquo;, &ldquo;10&rdquo; and &ldquo;11&rdquo;, a search object data is stored in first through fourth banks respectively. A search tree of the search address is constructed so that four data of object for a next search are stored in different banks. Upon a search, an address for each bank is set according to the search tree so as to enable readout of data at the same time, thereby reducing time required for the search.

Binary data search method for selecting from among candidate data, and apparatus therefor

This invention provides an associative memory that includes a plurality of associative memory integrated circuits. Each of the associative memory integrated circuits includes a plurality of memory words and a data registration device. The data registration device stores a retrieval word into one of the plurality of memory words in response to control signal received from an external source if a first priority signal is not received from at least another one of the plurality of associative memory integrated circuits and if the one of the plurality of memory words is in an open state.

Associative memory having a data registration device

In an associative memory comprising a function to extend data width, for which match retrieval is to be conducted, up to a plurality of words, that is, a function to detect total match data when match is respectively detected for a plurality of continuous retrievals, power consumption can be reduced by making active only the necessary areas under the condition that the whole circuit is no longer required to be made active through execution of the current retrieval only to the blocks for which match is detected in the preceding retrieval during a plurality of continuous retrieving operations and/or its adjacent blocks.

Associative memory

An associative memory device is cascade-connected to form an associative memory. The associative memory device includes a retrieval result register for storing a retrieval result of the lo associative memory device and the retrieval result of the associative memory devices of an upstream side of the associative memory device. An identification code register stores an identification code that indicates whether the associative memory device is a last stage associative memory device of the cascade-connected associative memory devices. If the associative memory device is the last stage associative memory device, the retrieval result stored in the retrieval result register is output. The associative memory outputs the retrieval result only when a signal instructing an output of the retrieval result is received.

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Chiba, Japan

Masahiro Konishi