Other

Semiconductor Technology Academic Research Center

Masahiro Konda

Tadashi Shibata

Tadahiro Ohmi

Tatsuo Morimoto

Akira Nataka

A computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences and a semiconductor computing circuit achievable with simple circuitry and suitable for use in such a computing circuit or apparatus. The computing circuit capable of computing the absolute difference includes a large input selection circuit which outputs either a first signal or a second signal whichever is larger, a small input selection circuit which outputs either the first and second signals whichever signal is smaller, and a subtraction circuit which subtracts the output of the small input selection circuit from the output of the large input selection circuit The subtraction circuit includes a capacitor a first switch provided between a first terminal of the capacitor and the output of the large input selection circuit a second switch provided between the first terminal of the capacitor and the output of the small input selection circuit and a third switch provided between a second terminal of the capacitor and a terminal connected to a prescribed potential. The computing apparatus capable of computing the sum of absolute differences includes a plurality of such computing circuits, and computes the sum of the outputs of the computing circuits by using a summing circuit.

Computing circuit, computing apparatus, and semiconductor computing circuit

Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage. The semiconductor computing circuit comprises: a first MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate; a second MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate, and whose source electrode is connected to the source electrode of the first MOS transistor; a write circuit which, with a prescribed voltage applied to the control gates of the first and second MOS transistors, sets the potential at the floating gate of the first MOS transistor to a value equal to the first signal voltage and also sets the potential at the floating gate of the second MOS transistor equal to a value obtained by subtracting the first signal voltage from the prescribed voltage; and a difference voltage computing circuit for computing a voltage representing a value obtained by subtracting the second signal voltage from the prescribed voltage, and wherein: after setting the first and second MOS transistors by the write circuit, when the output voltage of the difference voltage computing circuit is applied to the control gate of the first MOS transistor while at the same time applying the second signal voltage to the control gate of the second MOS transistor, the absolute-value voltage representing the difference between the first signal voltage and the second signal voltage is output.

Semiconductor computing circuit and computing apparatus

The real time compression of moving images employing vector quantization is realized using simple hardware and with an optimal compression ratio with respect to the communication line capacity employed. In the operating system, which is provided with a first mechanism (202), comprising a plurality of groups of numerical values, a second mechanism (201), a first circuit (206), a second circuit (206), and a third circuit (210), the second circuit comprises a plurality of fourth circuits divided into two or more groups (210-213, 219, and 301), the fourth circuits have a plurality of input terminals and at least one output terminal, and a mechanism is provided having a structure wherein various signals expressing degrees of similarity are inputted into the plurality of input terminals, only that signal having the largest degree of similarity among the variety of signals expressing degrees of similarity which are inputted is outputted from the output terminal, and the output signal of a predetermined first group among the two or more groups is inputted into an input terminal of a second group, whereby only one first vector having the largest degree of similarity is selected.

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Sendai, Japan

Masahiro Konda