Shin-etsu Handotai Co., Ltd.

Shin-etsu Chemical Co., Ltd.

Masahiro Kato

Norihiro Kobayashi

Isao Yokokawa

Hiroji Aga

Nobuhiko Noto

Masaro Tamatsuka

Satoshi Oka

Akihiro Kimura

Takao Abe

Toru Ishizuka

Tohru Ishizuka

Masayuki Imai

Tomosuke Yoshida

Hideki Sato

Osamu Ishikawa

Ryuji Kono

Osamu Imai

A bonded semiconductor wafer provided with a single crystal silicon layer on a main surface, wherein the bonded semiconductor wafer has a base wafer composed of a silicon single crystal, and the bonded semiconductor wafer has a first dielectric layer, a polycrystalline silicon layer, a second dielectric layer, and the single crystal silicon layer above the base wafer in this order, with a bonding plane lying between the polycrystalline silicon layer and the second dielectric layer; and wherein a carrier trap layer is formed between the base wafer and the dielectric layer. This provides a bonded semiconductor wafer of a trap-rich type SOI substrate wherein the base wafer can be prevented from lowering the specific resistance due to impurities and influence of electric charge in the BOX oxide film, distortion of radio-frequency fundamental signals and crosstalk signals from one circuit to another circuit are decreased, and the mass-productivity is excellent.

Bonded semiconductor wafer and method for manufacturing bonded semiconductor wafer

A method for evaluating a semiconductor wafer includes detecting semiconductor wafer LPDs as an examination sample in two measurement modes, performing size classification of the LPDs, calculating a distance between detection coordinates and a relative angle in the two measurement modes, presetting determination criteria to determine each LPD as a foreign matter or killer defect in accordance with each classified size, detecting semiconductor wafer LPDs as an evaluation target in the two measurement modes, performing size classification of the LPDs as the evaluation target, calculating a distance between detection coordinates and a relative angle of the evaluation target, and classifying the LPDs detected on a surface of the evaluation target into the killer defect and the foreign mater based on a result of the calculation and the determination criteria. The method enables classifying all LPDs from which quantitative size information cannot be provided, into the killer defect and foreign matter.

Method for evaluating semiconductor wafer

A method for heat treatment of a plurality of semiconductor wafers horizontally placed on a supporting member coated with SiC in a vertical heat treatment furnace includes performing heat treatments while switching the supporting member and a heat treatment condition such that the supporting member is continuously used in a heat treatment under either one of a first condition and a second condition for a certain period of time and then continuously used in a heat treatment under the other condition for a certain period of time, wherein the heat treatment under the first condition is performed at 1000&#xb0; C. or higher in an atmosphere containing a rare gas and not containing oxygen, and the heat treatment under the second condition is performed at 1000&#xb0; C. or higher in an atmosphere containing oxygen and not containing a rare gas. As a result, slip dislocation can be inhibited.

Heat treatment method

A method of producing a bonded wafer in which wafers each having a cutout portion are used as a bond wafer and a base wafer, and either or both of settings of an ion implanter with which ions are implanted and conditions of the ion implantation are adjusted in the step of implanting the ions such that a cutout portion of either or both of the bond wafer and the base wafer after bonding is located at within a range of 0&#xb1;30&#xb0; or 180&#xb1;30&#xb0; from a position at which separation of the bond wafer begins in the step of separating the bond wafer. This method can inhibit the occurrence of large fault defect that may be generated on a surface of a thin film right after the separation, when a thin film such as an SOI layer is formed by the ion implantation separation method.

Method of producing bonded wafer

According to the present invention, there is provided a method for manufacturing an SOI wafer having the step of performing a first sacrificial oxidation treatment on the aforementioned bonded SOI wafer in which the delamination has been performed after a first RTA treatment has been performed thereon and then performing a second sacrificial oxidation treatment thereon after a second RTA treatment has been performed thereon, wherein the first and second RTA treatments are performed under a hydrogen gas containing atmosphere and at a temperature of 1100&#xb0; C. or more, wherein after a thermal oxide film has been formed on the aforementioned SOI layer front surface by performing only thermal oxidation by a batch type heat treating furnace at a temperature of 900&#xb0; C. or more and 1000&#xb0; C. or less in the first and second sacrificial oxidation treatments, a treatment for removing the thermal oxide film is performed.

Method for manufacturing a bonded SOI wafer

A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.

Method for manufacturing SOI wafer

A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle &#x3b8; in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle &#x3c6; in a [01-1] direction or a [0-11] direction from the (100) plane, the angle &#x3b8; and the angle &#x3c6; are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1&#xd7;10/cm. Even when an epitaxial layer having a dopant concentration of 1&#xd7;10/cmor more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.

Silicon epitaxial wafer, method for manufacturing the same, bonded SOI wafer and method for manufacturing the same

The present invention is directed to a method for producing a bonded wafer, the method in which heat treatment for flattening the surface of a thin film is performed on a bonded wafer made by the ion implantation delamination method in an atmosphere containing hydrogen or hydrogen chloride, wherein the surface of a susceptor on which the bonded wafer is to be placed, the susceptor used at the time of flattening heat treatment, is coated with a silicon film in advance. As a result, a method for producing a bonded wafer is provided, the method by which a bonded wafer having a thin film with good film thickness uniformity can be obtained even when heat treatment for flattening the surface of a thin film of a bonded wafer after delamination is performed in the ion implantation delamination method.

Method for producing bonded wafer

There are provided a silicon wafer for epitaxial growth wherein a void type defect is not exposed on the surface where an epitaxial layer is grown, and a method for producing an epitaxial wafer comprising measuring the number of the void type defects exposed on the surface of a silicon wafer and/or the number of the void type defects which exist in the part to the depth of at least 10 nm from the surface of the silicon wafer, choosing the silicon wafer wherein the number of these void type defects is smaller than the predetermined value, and growing an epitaxial layer on the surface of the chosen silicon wafer. Thereby, there can be provided a silicon wafer for epitaxial growth wherein generation of SF is reduced and epitaxial wafer, and a method for producing it.

Silicon wafer for epitaxial wafer, epitaxial wafer, and method of manufacture thereof

The present invention provides a CZ silicon wafer, wherein the wafer includes rod-like void defects and/or plate-like void defects inside thereof, and a CZ silicon wafer, wherein the silicon wafer includes void defects inside the wafer, a maximum value of a ratio between long side length L and short side length L (L /L ) in an optional rectangle circumscribed the void defect image projected on an optional &lcub;110&rcub; plane is 2.5 or more, and the silicon wafer including rod-like void defects and/or plate-like void defects inside the wafer, wherein a void defect density of the silicon wafer at a depth of from the wafer surface to at least 0.5 &mgr;m after the heat treatment is &frac12; or less than that of inside the wafer. According to this, the silicon wafer, which is suitable for expanding reducing effect of void defects by heat treatment up to a deeper region, can be obtained.

Silicon wafer

There is disclosed a heat treatment method for a silicon monocrystal wafer comprising the steps of heat-treating in a reducing atmosphere a silicon monocrystal wafer manufactured by growing a silicon monocrystal ingot by Czochralski method wherein a wafer obtained from a silicon monocrystal ingot having oxygen concentration of 16 ppma or less which is manufactured by pulling at a growth rate of 0.6 mm/min or more, and in which COPs exist in high density is subjected to anneal heat treatment at 1200&deg; C. or above for one second or more through use of a rapid heating/rapid cooling apparatus, or at 1200&deg; C. or above for 30 minutes or more through use of a batchwise heat treatment furnace, and no defect silicon monocrystal wafer obtained with the method. There can be manufactured a silicon monocrystal wafer in which crystal defects existing on the surface of the wafer or at the surface layer portion thereof are minimized, and there can be provided a silicon monocrystal wafer for a device which is excellent in electric characteristics such as oxide dielectric breakdown voltage and electrical reliability.

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Takasaki, Japan

Masahiro Kato