Hitachi, Ltd.

Other

Hitachi Ulsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Masahiro Katayama

Shuichi Miyaoka

Hiroshi Akasaki

Masatoshi Hasegawa

Kanji Oishi

Shoji Kubono

Toru Kobayashi

Masaya Muranaka

Yukihide Suzuki

Makoto Morino

Yuji Yokoyama

Sinichi Miyatake

Shoji Wada

Masahiro Ogata

Kanehide Kenmizaki

Yousuke Tanaka

Miki Matsumoto

Yoshihisa Koyama

Hidetomo Aoyagi

Tetsuya Kitame

Nobuhiko Ohno

Kazufumi Watanabe

Seiichi Shundo

Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.

Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device

The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK to MBKn). A plurality of serial data readout from the memory cell array ( ) and parallel/serial converted by a parallel/serial converter circuit ( ) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit ( ) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.

High speed clock synchronous semiconductor memory in which the column address strobe signal is varied in accordance with a clock signal

A semiconductor memory incorporating an operation circuit for carrying out logical operations on data and arithmetic operations on address signals. The memory is arranged functionally so that the data representing the result of each of such operations is written to a memory array while also being output through an external terminal in the same memory cycle.

Semiconductor memory

A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input/output circuit corresponding to a defective chip address; a data input/output portion for selectively activating an input/output circuit to be connected to a data bus corresponding to a dynamic RAM found defective; and a mask portion for outputting a control signal for putting in a high-impedance state an output pin of the defective RAM in a read operation.

Semiconductor memory system

Growing community of inventors

Maebashi, Japan

Masahiro Katayama