Kabushiki Kaisha Toshiba

Amano Corporation

Masahiro Kanazawa

Kimiyoshi Usami

Naoyuki Kawabe

Toshiyuki Furusawa

Masayuki Koizumi

Hidemasa Zama

Daisuke Sonoda

Hiroshi Tanaka

Takashi Ishikawa

Mutsunori Igarashi

Takeshi Kitahara

Chiharu Mizuno

Masaaki Yamada

Katsuhiro Seta

Takeshi Miyashita

Yukiko Ito

An automatic circuit design apparatus includes a setting module configured to set an upper limit electric potential of a virtual ground line in a circuit to be designed, by use of a cell library for low-threshold cells, a cell library for high-threshold cells, and information of the circuit to be designed. A layout generator is configured to generate a layout based on the information, the cell library for low-threshold cells, and the cell library for high-threshold cells.

Automatic circuit design apparatus, method for automatically designing a circuit, and computer program product for executing an application for an automatic circuit design apparatus

A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Semiconductor integrated circuit with reduced leakage current

A semiconductor integrated circuit is disclosed, which comprises a tree structure of buffer circuit groups configured to have an enable-signal-controlled AND buffer circuit at least in a final stage, a latch circuit provided in a correspondence to the enable-signal-controlled AND buffer circuit and configured to receive an enable signal and clock signal and deliver an output to an input portion of a final stage buffer circuit, an enable-signal-controlled AND buffer circuit provided in a portion of an intermediate stage of the buffer circuit groups, and an OR circuit provided in a correspondence to the intermediate stage enable-signal-controlled AND buffer circuit and configured to take a logical sum of a plurality of enable signals for controlling the operations of a plurality of enable-signal-controlled AND buffer circuits more on a load circuit side and deliver a logical sum output to an input portion of the intermediate stage enable-signal-controlled AND buffer circuit.

Semiconductor integrated circuit and circuit designating system

A logic circuit design equipment and a logic circuit design method include analyzing input states of all of first cells, respectively, analyzing leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively, and substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.

Logic circuit design equipment and method for designing logic circuit for reducing leakage current

Semiconductor integrated circuit, logic operation circuit, and flip flop

A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefor in which a first cell to which multiple supply voltages are supplied is extracted (Step S ), the extracted cells are divided into groups (Step S ), cells for voltage supply are added and arranged according to the number of the groups (Step S ), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S ).

SEMICONDUCTOR INTEGRATED CIRCUIT, SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECORD MEDIUM FOR STORING PROGRAM OF SUPPLY METHOD FOR SUPPLYING MULTIPLE SUPPLY VOLTAGES IN SEMICONDUCTOR INTEGRATED CIRCUIT

Semiconductor circuit having a combination circuit being switched between an active and inactive state

An automatic circuit generation methods and apparatus ( ) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.

Automatic circuit generation apparatus and method, and computer program product for executing the method

There are disclosed a multi power supply integrated circuit evaluating method which is capable of detecting power supply voltage illegal connection, redundant connection, and potential redundant connection from connection descriptions contained in a multi power supply integrated circuit in the stage of circuit design and then correcting automatically such connections, and a system for embodying the same. The evaluating method comprises at least the steps of inputting a database in which various cells are registered and the connection descriptions of the multi power supply integrated circuit, detecting connections corresponding to the power supply voltage illegal connection, the redundant connection, and the potential redundant connection, registering the detected connections as the power supply voltage illegal connection, the redundant connection, and the potential redundant connection, outputting the power supply voltage illegal connection, the redundant connection, and the potential redundant connection, and correcting automatically the power supply voltage illegal connection, the redundant connection, and the potential redundant connection.

Multi-power supply integrated circuit evaluation system and method of operating the same

A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefore in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).

Semiconductor integrated circuit and supply method for supplying

There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.

Multi-power supply integrated circuit and system employing the same

A reversing board 14 with a magnetic head 16 mounted thereon is provided at its central portion with card guides 14b1, 14b2 , the inlet ports of the card guides 14b1, 14b2 being disposed proximate to the front end openings of front and rear card guides 2A, 2B, the magnetic head 16 being biased by a compression spring 17S so that the head can be acted upwardly and downwardly, a positioning stopper 15 being engaged in a positioning groove 14a of the reversing board 14, a rotational tension force being exerted to a head reversing gear 12 by a tension spring 13S.

Growing community of inventors

Yokohama, Japan

Masahiro Kanazawa