Kabushiki Kaisha Toshiba

Masahiro Kamoshida

Daisaburo Takashima

Haruki Toda

Yukihito Oowaki

Tsuneaki Fuse

Shigeo Ohshima

Koji Kato

Akira Umezawa

Takahiko Sasaki

Hironobu Akita

Katsumi Abe

Hiroyuki Ohtake

Katsuaki Sakurai

According to one embodiment, there is provided a semiconductor memory device including a memory cell array, a plurality of signal lines, and a plurality of signal-line-lead-out portions. In the memory cell array, a plurality of memory cells are arranged. The plurality of signal lines connected to the plurality of memory cells. The plurality of signal-line-lead-out portions are arranged in a periphery of the memory cell array and are connected to the plurality of signal lines. Each of the plurality of signal-line-lead-out portions includes a plug as an electrode whose upper surface and side surface are covered with a passivation film.

Semiconductor memory device

According to one embodiment, a resistance-change memory includes a memory element in which its variable resistance state corresponds to data to be stored therein, a pulse generation circuit which generates a first pulse, a second pulse, a third pulse, and a fourth pulse, the first pulse having a first amplitude which changes the resistance state of the memory element from a high- to a low-resistance state, the third pulse having a third amplitude smaller than the first amplitude to read data in the memory element, the fourth pulse having a fourth amplitude between the first amplitude and the third amplitude, and a control circuit which controls the operations of the memory element and the pulse generation circuit. The control circuit supplies the fourth pulse to the memory element after supplying the first pulse to the memory element.

Resistance-change memory and method of operating the same

A semiconductor integrated circuit device operates using a first power supply and a second power supply differing from the first power supply in voltage. The semiconductor integrated circuit device includes a first detecting circuit which detects that the first power supply has exceeded a specific voltage, a second detecting circuit which detects that the second power supply has exceeded a specific voltage, and a check circuit which checks the operating state of an analog circuit carrying out an analog operation using the first power supply and outputs a control signal indicating whether the analog circuit is operating properly. The detecting level of the first detecting circuit is determined on the basis of the control signal. A power-on reset signal is output according to the result of the detection at the first and second detecting circuits.

Semiconductor integrated circuit device with power-on reset circuit for detecting the operating state of an analog circuit

A semiconductor memory device includes memory cells, a memory cell array, word lines, a row decoder, first metal wiring layers, and metal wiring lines. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. Each word line is formed by connecting commonly the control gates in a same row. The row decoder selects any one of the word lines. The first metal wiring layers are provided for the word lines in a one-to-one correspondence. The first metal wiring layers are electrically connected to the corresponding ones of the word lines and transmit a first row select signal for the row decoder to select one of the word lines. The metal wiring lines are formed at a plurality of levels. The first metal wiring layers are made of the metal wiring lines located at the level of the lowest layer.

Semiconductor memory device with MOS transistors each having floating gate and control gate

A ferroelectric memory device includes a first bit line, a second bit line provided adjacent to the first bit line, a first memory cell block including a first terminal, a second terminal, and a plurality of memory cells connected in series between the first and second terminals and arranged in a first direction along the first bit line connected to the first terminal by a first block select transistor, a second memory cell block including a plurality of memory cells, and a plurality of first contacts arranged between the first and second memory cell blocks, each first contact connecting the upper electrode and drain or source electrode of one memory cell.

Ferroelectric memory device

A memory device comprises a normal memory cell array and a spare memory cell array, in which memory cells each comprising a ferroelectric capacitor are arranged; a normal word line; a normal word line driver; a spare word line; a spare word line driver; an address input circuit to which an address signal is inputted; and a judging circuit which compares an input address with a faulty address and generates an output for selecting one of the normal and spare word line drivers according to the comparison. The normal and spare word line drivers are simultaneously selected by an output of the address input circuit to start driving the normal and spare word lines, and thereafter the normal and spare word line drivers are enabled by the output of the judging circuit to stop the driving of one of the normal and spare word lines and continue the other.

Ferroelectric memory device with a spare memory cell array

A semiconductor memory device includes a sense amplifier, a pair of bit lines connected to the sense amplifier, first and second memory cell arrays connected to the bit lines, respectively, and including a plurality of memory cells each having a cell transistor and a ferroelectric capacitor, and first and second select transistors connected to the bit lines between the sense amplifier and the first and second memory cell arrays. The device further includes a first equalizing circuit connected to the bit lines closer to the first and second memory cell arrays than the first and second select transistors.

Nonvolatile semiconductor memory device using ferroelectric capacitor

A semiconductor memory device includes first and second select transistors arranged on both sides of a shared-scheme sense amplifier and connected to a bit line, and first and second memory cell arrays connected to the bit line via the first and second select transistors, respectively, the first and second memory cell arrays each including a plurality of memory cells each having a cell transistor and a ferroelectric capacitor. The device further includes a setting circuit which controls the first and second select transistors, thereby setting the first and second memory cell arrays in an operative state at the same time, and a control circuit which performs a test at the same time for the first and second memory cell arrays, which are set in the operative state at the same time by the setting circuit.

Shared sense amplifier scheme semiconductor memory device and method of testing the same

Each delay unit is divided into two delay unit groups, the preceding stage side and the succeeding stage side. To the delay unit group in the preceding stage side, power supply voltage is supplied via a power supply terminal, and to each delay unit of the delay unit group in the succeeding stage side, power supply voltage is supplied from the power supply terminal via a power supply control switch. A forward-pulse detecting circuit detects that forward pulse was propagated to a stage between the N-th stage and a stage a predetermined number of stages before the N-th, and outputs the detected result to the power supply control switch. With this operation, when forward pulse is propagated to the (N&plus;1)th stage, power supply voltage is supplied also to the delay unit group in the succeeding stage side. As electric power is not supplied to the delay unit group in the succeeding stage side when forward pulse is not propagated to the (N&plus;1)th stage, wasteful consumption of electric power is prevented.

Apparatus comprising clock control circuit, method of controlling clock signal and device using internal clock signal synchronized to external clock signal

A state-holding circuit initializing circuit initializes state-holding circuit when propagation of forward pulse to the forward-pulse delay circuits in the last stage is detected. With this operation, synchronization is established in a short time from the resumption of outputting from a receiver. The state-holding circuit control circuit also controls the reset timing of the state-holding circuit. A forward-pulse adjusting circuit controls the pulse width of forward pulse to be supplied to the forward-pulse delay line. With this operation, the stages from the stage where rearward pulse was generated to the first stage are securely turned to the set state, enabling propagation of rearward pulse and synchronization is established. Thus, synchronization is established reliably even when output from a receiver stops or the duty of an external clock signal is heavy.

Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal

In this clock control circuit, clock signal CLK from a receiver is supplied to a pulse generating circuit, and the pulse generating circuit generates forward pulse, which is clock signal CLK delayed as much time as A, and pulse s which is synchronized with dock signal CLK and has a pulse width of A. Consequently, as forward pulse becomes &ldquo;H&rdquo; while pulse s is &ldquo;L&rdquo; without generating pulse which width is narrower than A, the edge part of forward pulse is securely propagated by a forward-pulse delay line even if it is high frequency. Propagation of forward pulse stops at rising edge of pulse s, and rearward pulse is generated in a corresponding stage. This rearward pulse is propagated by a rearward-pulse delay line, and outputted from an output buffer. As each delay element of forward-pulse delay line and rearward-pulse delay line is configured with one-gate circuits, propagation time of forward pulse and rearward pulse can be adjusted to the time (&tgr;&minus;A) with high accuracy to improve synchronization accuracy.

Clock control circuit

A semiconductor integrated circuit has an internal clock signal generator circuit and a data input/output circuit. The internal clock signal generator circuit includes a clock receiver, a synchronous delay control circuit, a clock driver, an output control circuit, a delay monitor, and a control signal generator circuit. Accordingly, in a delay measuring mode, a delay in the input signal is set in the delay monitor based on a measurement start signal and a measurement stop signal. After completion of the delay measuring mode, the delay monitor causes the signal CLK, outputted from the clock receiver, to lag behind by a delay set in the delay measuring mode. Further, the delay monitor outputs the delayed signal to the synchronous delay control circuit.

Synchronous type semiconductor integrated circuit having a delay monitor controlled by a delay control signal obtained in a delay measuring mode

A clock synchronous circuit comprising a clock receiver, a delay monitor, a forward pulse delay circuit, a backward pulse delay circuit, a driver, a state-holding section, a control signal generating circuit, a first AND circuit, and a second AND circuit. The delay monitor delays the output of the clock receiver. The forward pulse delay circuit delays the output of the delay monitor. The backward pulse delay circuit delays the output of the clock receiver. The driver receives the output of the backward pulse delay circuit and outputs an internal clock signal. The state-holding section controls the backward pulse delay circuit. The control pulse generating circuit initializes the forward pulse delay circuit. The first AND circuit is provided for controlling the supply of the output of the clock receiver to the delay monitor. The second AND is provided for controlling the supply of the output of the delay monitor to the forward pulse delay circuit.

A delay line for forward pulse has a plurality of delay units for forward pulse. A delay line for backward pulse has a plurality of delay units for backward pulse. In the delay line for backward pulse, a pulse signal is propagated in an opposite direction to a direction of the propagation in the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for forward pulse is set to be parallel to a direction of the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for backward pulse is set to be parallel to a direction of the delay line for backward pulse. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for forward pulse are set to be opposite to one another. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for backward pulse are set to be opposite to one another.

Delay control circuit synchronous with clock signal

A clock control circuit includes a forward pulse delay circuit including a plurality of delay circuits for delaying a forward pulse signal FCL, a backward pulse delay circuit including a plurality of delay circuits for delaying a backward pulse signal RCL, a state-hold section including a plurality of state-hold circuits for controlling the operation of the backward pulse delay circuit in accordance with the transmission condition of the forward pulse signal in the forward pulse delay circuit, and an input stop circuit for stopping inputting a pulse corresponding to an external clock signal to the backward pulse delay circuit during a predetermined period from the time point when the external clock signal begins to be supplied.

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Yokohama, Japan

Masahiro Kamoshida