Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer System, Ltd.

Other

Renesas Technology Corp.

Masahiro Kainaga

Mitsuru Watabe

Shiro Baba

Yasushi Akao

Kouki Noguchi

Keiichi Kurakazu

Takanaga Yamazaki

Shumpei Kawasaki

Toshimasa Kihara

Takashi Tsukamoto

Yugo Kashiwagi

Shigeki Masumura

Kaoru Fukada

Eiji Sakakibara

Yoichi Asano

Katsuhiko Ishida

Yasuhiro Tawara

Shuya Fujita

Noriko Sawa

Hideaki Chaki

Tadahiko Sugawara

Kousuke Sakoda

Ichiro Kyushima

Hidehiko Akita

Koji Yamada

Tohru Nojiri

Hiroaki Nakanishi

Fumiya Murata

Yoshitake Nakaosa

Masaharu Yabushita

Yasuhiko Saito

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Microcomputer and dividing circuit

A data processing method for compressing vertex coordinate data of a plurality of polygons approximating a three-dimensional shape of an image, an apparatus therefor, and a program recording medium therefor. Vertexes of a plurality of polygons approximating a three-dimensional shape of an image are divided into a plurality of vertex sets. A reference point is defined for each of the vertex sets. As positional information of each vertex in each of the vertex sets, differential data between the coordinates of the vertex and the coordinates of the reference point is obtained as an integer value indicating the magnitude relative to a predetermined scale value. The coordinate data of the reference point and the differential data in each of the vertex sets are compressed data.

Data processing method, recording medium and data processing apparatus

A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation

A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word

A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.

Branch instruction having different field lengths for unconditional and conditional displacements

Microcomputer having variable bit width area for displacement

Central processing unit having instruction queue of 32-bit length

Particular portions of a program is determined to execute repeatedly. Array references accessed in a loop are classified to groups of equal values on the basis of reference to the same array. Of the groups, the ones for which an array transposition can use a batch load or store instruction are selected. An array corresponding to the selected groups is transposed to generate an intermediate language for copying. Reference to the elements of the array before the transposition is changed to reference to the transposition array. This makes it possible to convert the loop so that a single instruction can be used for a processor which can load into a register two data having consecutive addresses in a memory with use of the instruction.

Compiling method of accessing a multi-dimensional array and system

Microcomputer having variable bit width area for displacement and

A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acquire a new partial remainder. The division is repeated a predetermined number of times in which a quotient bit is acquired according to the sign of the acquired partial remainder or the divisor. The dividend is corrected by subtracting 1, which is the significance of an LSB of the corresponding dividend, from the dividend when the sign of the dividend is negative, and the corrected dividend is used for the division processing.

Division circuit and the division method thereof

Microcomputer having 16 bit fixed length instruction format

A control system for a cache provided between a central processing unit and a main memory. The control system includes a plurality of entries each having a data area and a control information area. A reuse information field in the control information area is set at the same time as a load/store instruction from the central processing unit. When the central processing unit issues an access instruction to desired data in the main memory, an entry storing the desired data to be accessed is searched from a plurality of entries of the cache. If the desired data is not present in any of the plurality of entries, the desired data is read from the main memory. Then, an empty entry is searched from the plurality of entries. If there is no empty entry, an entry is selected which is not set with the reuse information in the control information area of the entry, the reuse information instructing to preferentially maintaining the data in the data field of the entry. The data of the selected entry is replaced by the data read from the main memory. Reuse information in an access command from the central processing unit for maintaining data in a particular entry is set to the reuse information field.

Cache reuse control system having reuse information field in each cache

A multiprocessor having a plurality of processor elements connected in a cascaded manner. A memory is shared between each processor element and a processor adjacent in an upper or lower rank to the processor. In the lower processor element, there are disposed an arbiter for arbitrating a memory access with its upper processor element and a bus selector for switching a bus with the arbiter. The processor elements are connected in a multistage tree structure by a bus connection only. From the upper processor element, therefore, there can be accessed the shared memory in the lower processor element only through an external bus. The whole system is not limited by the address space of each processor and the bus, even if the address space is finite, so that the real memory capacity can be limitlessly expanded in a manner to correspond to the internal memory of each processor element.

Hierarchy structured memory system contained in a multiprocessor system

In an adder control circuit, a plurality of full adders are so arranged that a carry bit of the full adder for calculating low orders of values to be added is inputted to the full adder for calculating high orders thereof. In this case, the addresses are controlled in response to a clock having a time period which is more than a maximum calculation time period among calculation time periods by the respective full adders required for outputting the carry bits, and is less than a total calculation time period of all full adders.

Adder control method and adder control circuit

Growing community of inventors

Yokohama, Japan

Masahiro Kainaga