Fuji Xerox Co., Ltd.

Fujifilm Business Innovation Corp.

Masahiro Ishiwata

Yoshihiro Terada

Kazuman Taniuchi

Katuyuki Kouno

Kazuyasu Sasuga

Kazuo Yamada

Hiroshi Sekine

Yoshinori Awata

Keiichi Ito

Junichi Uchiyama

Mitsuyuki Tamatani

Teruyuki Aoyama

Tsutomu Nagaoka

Masatomo Igarashi

Noriaki Tsuchiya

Hirofumi Sasaki

Tatsuji Shimizu

Ryo Kukimiya

Akihiko Fusatani

Takeshi Suda

An information processing apparatus includes a processor connected to a programmable logic circuit. The processor is configured to: upon initialization, reconfigure a first region of the programmable logic circuit as a first memory that stores data; reconfigure a second region different from the first region of the programmable logic circuit as a first arithmetic circuit that uses the first memory; and, in a case where the second region reconfigured as the first arithmetic circuit is reconfigured as a second arithmetic circuit different from the first arithmetic circuit, allow the second arithmetic circuit to use the first memory.

Information processing apparatus and non-transitory computer readable medium

A reconfigurable logical circuit includes a data processing unit; a memory in which plural combinations of configuration control bits are stored; and a selector unit that selectively switches the plural combinations of configuration control bits stored in the memory and supplies a selected one of the plural combinations of configuration control bits to the data processing unit to reconfigure processing contents of the data processing unit.

Reconfigurable logical circuit

An information processing apparatus includes a dynamic reconfiguration device and a processor. The dynamic reconfiguration device has a first region with a static configuration, a second region with a changeable configuration, a switch used for bypassing between input and output terminals of the second region, and a crossbar switch used for switching a connection between the first region and the second region. The processor is configured to set a writing destination for a circuit to be reconfigured based on a resource to be used by the circuit if the circuit is to be written in the second region.

Information processing apparatus, dynamic reconfiguration device, and non-transitory computer readable medium

An electronic apparatus includes the following elements. A circuit forming device forms a circuit configured in accordance with configuration information. A first storage unit stores first configuration information externally obtained via a first communication line. The first configuration information is used for forming a first circuit implementing a function including a first communication function in the circuit forming device. A second storage unit stores second configuration information different from the first configuration information. The second configuration information is used for forming a second circuit implementing a function including the first communication function in the circuit forming device. A recovery controller performs control so that the second circuit is formed in the circuit forming device by using the second configuration information, upon the occurrence of an error in communication via the first communication line when the first circuit is formed in the circuit forming device by using the first configuration information.

Electronic apparatus

An image processing apparatus is disclosed which is connected to external machines for inputting data therefrom to a plurality of image memories and outputting data from the plurality of image memories thereto. The image processing apparatus includes a plurality of memory access controllers connected to the plurality of image memories, and a control device for selecting, a first mode for the plurality of memory access controllers to access the image memories separately, or a second mode for a master controller, which is one of the memory access controllers, to access the plurality of image memories as one image memory space so a to control the plurality of memory access controllers.

Image processing apparatus for processing digital signals

In an image input/output control apparatus having three lines of n-bit bidirectional data buses provided on an external apparatus connection side of the apparatus and four lines of n-bit bidirectional data buses provided on an image memory side of the apparatus, there are provided a first inner register for setting the data transfer direction of each of the bidirectional data buses and a second inner register for setting an image valid area, whereby the data transfer direction of each of the bidirectional data buses is determined by a set point of the first inner register and the image valid area is determined by a set point of the second inner register.

Apparatus for data transfer between image memory and external I/O device

A texture image processing system for image processing apparatus comprises, first calculator for calculating a maximum value and a minimum value of texture image data; second calculator for calculating an average value and a gain value with employment of said maximum value and minimum value; and synthesizing processor for synthesizing texture image data by image picture data, this synthesizing processor synthesizing the texture image data with the image picture data by multiplying a difference between the texture image data and the average value by the gain value. Also, synthesizing processor synthesizes the texture image data with chromaticity information of the image picture data, or chromaticity information of the image picture data with predetermined chromaticity information, chromaticity information of the texture image data. With the above-described structures, both of hue and saturation in the image picture data are maintained, and also the synthesized texture image having no great brightness change over its entire region is obtained.

Image processing apparatus for combining image data and texture image

An image processing system assigns weight factors to two respective image signals of the equivalent color space so that the two image signals are combined according to the respective weight factors. For example, two weight factors having a sum of unity are assigned to the respective image signals. Alternatively, two weight factors are assigned independently.

Image combining in image processing apparatus

A reduction/enlargement processing system for an image processing apparatus of the type in which a line sensor is moved in a secondary scan direction while an image on an original is read by the line sensor in a main scan direction, comprising, line buffers for retaining image data for two lines, an interpolation processing circuit for applying a 2-point interpolation to the image data when the image data is written into or read out of the buffers, and a control circuit for controlling the writing data to and read data from the buffers and the interpolation circuit. Further, selectors are provided on the data input side and the data output side, and on the buffer side. The interpolation circuit is connected between the selectors. The line buffers are alternately selected for the read/write of image data. With use of the selectors, the 2-point interpolation may be applied to the image data or the image data may be directly processed. This provides a simple data processing that is performed in accordance with the reduction/enlargement mode.

Reduction/enlargement processing system for an image processing apparatus

Conversion/non-conversion of input image data into replacing color data is controlled by a color converting system to produce output image data. Color detecting means detects a comparision color from the input image data by judging whether the input image data is within a preset comparison color range. Selecting means selects and outputs the input image data or the replacing color data provided by replacing color means on the basis of a judgment in the color detecting means.

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Kanagawa, Japan

Masahiro Ishiwata