Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electronics Corporation

Masahiro Ishida

Masaaki Yuri

Osamu Imafuji

Kenji Orita

Shinji Nakamura

Masahiro Ogawa

Tetsuzo Ueda

Kenichiro Tanaka

Daisuke Shibata

Satoshi Tamura

Daisuke Ueda

Shinichi Kohda

Ryo Kajitani

Tadao Hashimoto

Kunio Itoh

Masaya Mannoh

Naohide Wakita

Yasuhiro Yamada

Hirokazu Shimizu

Hidekazu Umeda

Shinichi Takigawa

Junko Iwanaga

Tetsuya Takayanagi

Jun Shimizu

Kenzi Orita

A liquid treatment apparatus includes a liquid storing vessel, a first electrode, a second electrode at least partly arranged inside the vessel, a tubular first insulator surrounding a first-electrode lateral surface with a first space interposed therebetween, and including a first opening in an end surface in contact with the liquid, a tubular second insulator surrounding the first-electrode lateral surface inside the first insulator, a gas supply device supplying gas into the first space and ejecting the gas into the liquid through the first opening, and a power supply applying a voltage between the first and second electrodes and producing plasma. The second insulator is arranged with a second space interposed between the first and second insulators. Portions of the first and second insulators, those portions being positioned inside the vessel, are covered with the gas when the gas is supplied into the first space by the gas supply device.

Liquid treatment apparatus including first electrode, second electrode, and first and second insulators surrounding lateral surface of first electrode

A field effect transistor having a reduced sheet resistance is provided. A channel layer, a first spacer layer, a second spacer layer, a first electronic barrier layer, and a second electronic barrier layer are sequentially grown on the main surface of a substrate. A gate recess is created, and then an ion implanted section is formed. A third electronic barrier layer and a p-type layer are formed by a metalorganic chemical vapor deposition (MOCVD) method. The p-type layer except a portion at the gate recess is removed. B ions are implanted in the regrown third electronic barrier layer to reform the ion implanted section. A source electrode and a drain electrode are formed on the third electronic barrier layer. Then a gate electrode is formed on the p-type layer.

Field effect transistor

A semiconductor device includes: a substrate; a drift layer which is disposed on the substrate and has a groove; an underlayer which is disposed above the drift layer; a first opening which penetrates the underlayer to reach the drift layer; an electron transit layer and an electron supply layer which are disposed to cover the first opening; a second opening which penetrates the electron supply layer and the electron transit layer to reach the underlayer; a gate electrode which is disposed above the electron supply layer at a position corresponding to a position of the first opening; a source electrode which is disposed to cover the second opening and in contact with the underlayer; and a drain electrode which is disposed on a backside surface of the substrate. A bottom surface of the groove is closer to the substrate than a bottom surface of the first opening.

Semiconductor device

A nitride semiconductor device includes: a substrate having a first major surface and a second major surface; a first nitride semiconductor layer of an n-type which is disposed on the first major surface and has a protrusion; a second nitride semiconductor layer of a p-type disposed on the protrusion; a first anode electrode disposed above the first nitride semiconductor layer and the second nitride semiconductor layer; and a cathode electrode disposed under the second major surface, and a lateral surface of the protrusion is inclined by a first angle with respect to the first major surface.

Nitride semiconductor device

A nitride semiconductor device includes: a substrate of a first conductivity type having a first surface and a second surface on a side of the substrate opposite the first surface; a first nitride semiconductor layer of the first conductivity type which is disposed on the first surface of the substrate and includes an acceptor impurity; a second nitride semiconductor layer of a second conductivity type disposed on the first nitride semiconductor layer, the second conductivity type being opposite to the first conductivity type; a first electrode disposed on the second surface of the substrate; a second electrode disposed on the first nitride semiconductor layer; and a gate electrode disposed on the second nitride semiconductor layer.

A nitride semiconductor device according to the present disclosure includes a substrate; a first nitride semiconductor layer which is formed on the substrate, and which has a C-plane as a main surface; a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and which has p-type conductivity; and a first opening which is formed in the second nitride semiconductor layer, and which reaches the first nitride semiconductor layer. The nitride semiconductor device further includes a third nitride semiconductor layer which is formed so as to cover the first opening in the second nitride semiconductor layer; a first electrode which is formed on the third nitride semiconductor layer so as to include a region of the first opening; and a second electrode which is formed on the rear surface of the substrate.

Provided is a semiconductor device in which electron mobility is improved by applying sufficiently large tensile stress in a predetermined direction without occurrence of cracks in a nitride semiconductor. The semiconductor device includes: substrate (), electron transit layer () that is disposed on substrate () and is formed by GaN; and electron supply layer () that is disposed on electron transit layer () and is formed by AlGaN. A coefficient of thermal expansion of substrate () is different between a first direction in a main surface of substrate () and a second direction that is perpendicular to the first direction in the main surface, and tensile stress occurs in electron transit layer ().

A field-effect transistor includes a codoped layer made of AlGaN (0&#x2266;x&#x2266;1) and formed on a p-type Si substrate, a GaN layer formed on the codoped layer, and an AlGaN layer formed on the GaN layer. The codoped layer contains C and Si as impurity elements. The impurity concentration of C in the codoped layer is equal to or higher than 5&#xd7;10/cm. The impurity concentration of Si in the codoped layer is lower than the impurity concentration of C. The impurity concentration of C in the GaN layer is equal to or lower than 1&#xd7;10/cm. The thickness of the GaN layer is equal to or greater than 0.75 &#x3bc;m.

Field-effect transistor

An object of the present invention is to provide a nitride semiconductor device and a nitride semiconductor substrate in each of which a nitride semiconductor layer formed on a silicon substrate is improved in crystallinity to realize a decrease in on-resistance of a field-effect transistor. The nitride semiconductor device includes a silicon substrate, and a first nitride semiconductor layer formed over the silicon substrate and including a nitride semiconductor, wherein a Si &#x3c;111&#x3e; axial direction of the silicon substrate is different from a &#x3c;0001&#x3e; axial direction of the first nitride semiconductor layer.

Nitride semiconductor device and nitride semiconductor substrate

A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 &#x3a9;cm or more, and the internal region has a resistivity of 1000 &#x3a9;cm or more.

Nitride semiconductor structure

A first group III nitride semiconductor layer has a low carbon concentration region having a carbon concentration of less than 1&#xd7;10cm, and located in a region under an edge of a gate electrode closer to a drain electrode, a thickness dof the low carbon concentration region satisfies/(110&#xb7;1)&#x2266;2&#x3c;/(110&#xb7;1)+0.5

Heterojunction field-effect transistor with field plate connected to gate or source electrode

A nitride semiconductor element includes: a strain suppression layer formed on a silicon substrate via an initial layer; and an operation layer formed on the strain suppression layer. The strain suppression layer includes a first spacer layer, a second spacer layer formed on and in contact with the first spacer layer, and a superlattice layer formed on and in contact with the second spacer layer. The first spacer layer is larger in lattice constant than the second spacer layer. The superlattice layer has first layers and second layers smaller in lattice constant than the first layers stacked alternately on top of one another. The average lattice constant of the superlattice layer is smaller than the lattice constant of the first spacer layer and larger than the lattice constant of the second spacer layer.

Nitride semiconductor element

A nitride semiconductor device includes: a semiconductor substrate; a p-type semiconductor layer formed over the semiconductor substrate, made of a nitride semiconductor, and containing first impurities; and an insulating film contacting the p-type semiconductor layer and having an impurity region containing second impurities for trapping hydrogen. Since residual hydrogen in the p-type semiconductor layer is trapped in the impurity region, the hydrogen concentration in the impurity region is higher than that in the insulating film excluding the impurity region.

Nitride semiconductor device and manufacturing method thereof

A manufacturing method for a semiconductor device formed in a device region composed of a plurality of semiconductor layers on a substrate, the method including a trench forming step of forming a trench on the substrate around the device region and a semiconductor growth step of growing the semiconductor layer in the device region.

Manufacturing method for semiconductor device, semiconductor device and semiconductor wafer

A semiconductor substrate comprises a semiconductor layer comprising a group III nitride as a main component. A scattering portion for scattering an incident beam of light incident on one plane of the semiconductor layer is provided on another plane or inside of the semiconductor layer.

Growing community of inventors

Osaka, Japan

Masahiro Ishida