Fujitsu Corporation

Masahiro Ise

Osamu Ishibashi

Masazumi Maeda

Jin Abe

Michiyo Garbe

Yoshinori Mesaki

A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.

Memory control circuit, memory, and memory control method

A memory includes a memory cell including a memory transistor in which electric charges are stored in an electric charge storage layer when data is written to the memory cell, and a controller configured to control a voltage to be applied to the memory transistor in a predetermined hold time until an amount of electric charges stored in the electric charge storage layer decreases to an amount of electric charges corresponding to a state where the data is erased from the memory cell.

Memory and memory control method

A memory device comprises a memory block including a plurality of cells each including an erase state and a program state, respectively; and a control circuit configured to execute, in response to a program command, program operation of applying a pulse to each cell to charge an electric charge and transferring the cell from the erase state to the program state. The control circuit executes, in response to a diagnostic command, diagnostic operation of applying to a diagnostic target cell the pulse within a range that the diagnostic target cell in the erase state in a memory block including stored data is not shifted to the program state, and checking whether or not a charge speed of the diagnostic target cell is faster than or equal to a charge speed of a slowest-speed cell whose charge speed is the slowest among normal cells.

Memory device, storage apparatus and method for diagnosing slow memory cells

When an address indicating an access destination of a data storing unit, and a command indicating a content of a process for the address are input, block information corresponding to the input address is output from an information holding unit. Whether or not to execute the command for the address is decided on the basis of the output block information and the input command.

Semiconductor storage device and control method thereof

An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit.

Nonvolatile memory unit with secure erasing function

In a semiconductor storage apparatus, an internal address generation unit generates, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address. When receiving the successive external addresses, a memory cell connected to the same bit line and word line is not continuously selected, and erroneous readout due to rewriting of a value of the memory cell in a non-selected state is suppressed.

Semiconductor storage apparatus and semiconductor integrated circuit

A nonvolatile memory wherein remaining lifetimes of memory cells can be accurately determined is provided, the nonvolatile memory includes: plural memory cell groups, assigned with respective addresses, arranged for respective words and used for storing one word of data; plural dummy cell groups also assigned the respective addresses and having different ranks of rewriting lifetimes; a writing circuit which, when writing data into a memory cell group having a given address, also writes the data into a dummy cell group having the same address at the same time; a lifetime recognizing circuit which recognizes an estimated number of past writing times by determining whether each dummy cell group can be successfully accessed; and a control section which controls operations of the memory cell groups and the dummy cell groups in response to an externally given command.

Nonvolatile memory comprising a circuit capable of memory life time recognizing

A magnetic resistance memory includes an identity determining unit that compares, bit by bit, first data stored in an address specified by a write request with second data to be written to the address, and that determines whether bit-by-bit values of the first data and the second data are identical; and a writing control unit that halts, when a bit of the second data is identical with a corresponding bit of the first data, writing of the bit of the second data.

Growing community of inventors

Machida, Japan

Masahiro Ise