Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Nuvoton Technology Corporation Japan

Panasonic Semiconductor Solutions Co., Ltd.

Masahiro Higuchi

Hiroshi Fujinaka

Sanshiro Shishido

Yutaka Abe

Kazuko Nishimura

Makoto Ikuma

Yuusuke Yamaoka

Dai Ichiryu

Hiroshi Kimura

Kenichi Origasa

Hiroyuki Amikawa

Takayasu Kito

An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.

Solid-state imaging device and class AB super source follower

A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.

Solid-state imaging device, and camera system using same

A solid-state imaging device that suppresses streaking includes an imaging region in which unit cells are aligned in matrix, an A/D converter for converting an analog signal generated in the imaging region to a digital signal, and a ramp buffer having an input terminal and an output terminal. Ramp voltage is input to the input terminal, and a reference signal having the ramp voltage is output from the output terminal toward the A/D converter. The A/D converter includes a comparator disposed in each column for comparing an analog signal with a reference signal, and a counter disposed corresponding to the comparator for counting a comparison period of the comparator. The ramp buffer includes a feedback circuit for simultaneously outputting the reference signal to the multiple comparators and controlling the amount of current flowing to the output terminal according to the ramp voltage of the reference signal output from the terminal.

Solid-state imaging device and imaging device

A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

Solid-state imaging device and imaging apparatus

The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.

Solid-state imaging device and camera for reducing random row noise

A ramp generator circuit includes: a reference signal generator circuit which generates a ramp waveform having a slope obtained by multiplication using a power of 2 according to a value of a higher order bit of a gain control signal; a clock control circuit which selectively outputs 2^m kinds of fractional-N clocks according to one of 2^m (natural number) areas obtained by dividing a code range represented by a lower order bit, when a negative gain is set; and a variable gain circuit which sets a ramp waveform according to the value of the gain control signal, and sets a ramp signal amplitude in each area so that a period ratio between ramp driving clocks for adjacent areas and a ratio between an amplitude of a ramp signal when the standard gain is set and a largest amplitude of a ramp signal are equal.

Ramp generator circuit and solid-state imaging device

Solid-state imaging device and camera

A voltage generation circuit includes a control circuit which outputs a first digital signal, a DAC which outputs a first analog signal corresponding to the first digital signal, and an attenuator which is connected to an output terminal of the DAC and is configured to output a voltage signal obtained by attenuating the first analog signal input from the DAC.

Voltage generation circuit, analog-to-digital conversion circuit, solid-state imaging device, and imaging apparatus, which are capable of reducing random noise

The ramp-signal generator circuit includes a reference voltage generator that changes the voltage of a reference signal Vr to a comparator setting voltage VR for compensating for a voltage difference between a reference signal Vr and an analog input signal (Vs-Vsn) before comparison by an analog-to-digital converter circuit and outputs a ramp signal whose slope starts from the comparator setting voltage VR in response to a start of the comparison. The ramp-signal generator circuit is configured to add a predetermined enhanced voltage VA to the comparator setting voltage VR before the comparison.

Ramp-signal generator circuit, and image sensor and imaging system including the same

A solid-state imaging device including: a plurality of pixels which are on a same semiconductor substrate and each of which generates a pixel signal; a comparison circuit that is connected to the pixels in each of columns; a D/A conversion circuit that generates a comparison potential and provide the generated comparison potential in common to the comparison circuit in each column; and a D/A conversion circuit output unit provided in a common line for providing the comparison potential to the comparison circuit in each column, wherein the D/A conversion circuit output unit includes: a source follower circuit that is provided to the line and includes a first current source having a transistor, and an amplification transistor having a gate oxide film that is thinner than a gate oxide film of the transistor; and a voltage control circuit that controls a drain-to-source voltage of the amplification transistor.

Solid-state imaging device and image capturing apparatus including the same

A ramp wave output circuit includes a ramp wave generation circuit generating a ramp wave, and a low-pass filter having a variable cutoff frequency, which receives the ramp wave. The low-pass filter operates at a first cutoff frequency for a predetermined time period after the receipt of the ramp wave, and at a second cutoff frequency, which is larger than the first cutoff frequency, after the predetermined time period has passed.

Ramp wave output circuit, analog/digital conversion circuit, and camera

A first to a fourth sampling switch (to), a first to a fourth sampling capacitance (to), and a first and a second charge redistribution switch () are provided on the input side of a differential amplifier (). A first and a second reset switch () are provided between inputs and outputs of the differential amplifier (). A positive-polarity input signal voltage (Vinp), a negative-polarity comparison reference voltage (Vrefn), a positive-polarity comparison reference voltage (Vrefp), and a negative-polarity input signal voltage (Vinn) are applied via the first to fourth sampling switches (to) to one ends of the first to fourth sampling capacitances (to), respectively. During a reset period, the reset of the differential amplifier () is released after sampling of the voltages. During a comparison period, the first and second charge redistribution switches () are caused to be in a conduction state.

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Hyogo, Japan

Masahiro Higuchi