Seiko Epson Corporation

Masahiro Hayashi

Takafumi Noda

Akihiko Ebina

Kunio Watanabe

Masahiko Tsuyuki

Takahisa Akiba

Tomo Takaso

Susumu Kenmochi

Toshimichi Yamada

Kazuhiko Okawa

Hiroaki Nitta

Tatsuro Shinmitsu

Takahisa Akira

Akihiro Shiraishi

This semiconductor device includes: a semiconductor substrate of a first conductive type; a first impurity layer of a second conductive type that is formed on a surface of the semiconductor substrate; a second impurity layer of the first conductive type that is formed to surround the first impurity layer on the surface of the semiconductor substrate; an insulating film that covers at least the first impurity layer; a first resistive element that is spiral-shaped and is provided on the insulating film; a second resistive element that is provided on an outer side of the first impurity layer in a planar view of the semiconductor substrate; and a first wiring that couples an end portion of the first resistive element on an outer peripheral side thereof and the second resistive element to each other.

Semiconductor device and power source control IC

Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.

Drive control device, drive circuit, and vehicle

A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.

Semiconductor device

A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor layer, an insulated-gate field effect transistor provided in the semiconductor layer, an etching stopper film provided above the insulated-gate field effect transistor, and an interlayer insulating layer provided above the etching stopper film; the insulated-gate field effect transistor including a gate insulating layer provided on the semiconductor layer, a gate electrode provided on the gate insulating layer, and an impurity region that constitutes a source region or a drain region provided in the semiconductor layer; wherein a removed region made by removing the etching stopper film is provided in at least part of an area that is located outside the gate insulating layer and above an area at a position other than a position sandwiched by the gate insulating layer and the impurity region.

Semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor element, comprises: (1) forming a first insulating layer for electric field relaxation that is thicker than a first gate insulating layer in a first channel region of a transistor of a first conductive type that is one of P-type and N-type polarity formed on a semiconductor silicon wafer to surround an edge of a first gate electrode in order to reduce an electric field concentrated to a region surrounding the edge of the first gate electrode because of a voltage applied to the first gate electrode and a first drain region of the transistor of the first conductive type, and forming a second insulating layer for electric field relaxation that is thicker than a second gate insulating layer in a second channel region of a transistor of a second conductive type to surround the edge of the first gate electrode in order to reduce an electric field concentrated to a region surrounding an edge of a second gate electrode because of a voltage applied to the second gate electrode and a second drain region of the transistor of the second conductive type; (2) forming a first photoresist layer in an uppermost section of the wafer.

Method for manufacturing a semiconductor element

A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving transistor forming region.

Method for manufacturing semiconductor devices

A method is provided for manufacturing a semiconductor device that can reduce the number of steps in manufacturing a triple-well that includes multiple ion implantation steps and heat treatment steps. The method comprises the steps of: (a) forming a first mask layer having a first opening section on a semiconductor substrate; (b) forming a first dielectric layer on an exposed surface of the semiconductor substrate in the first opening section; (c) forming an impurity layer by introducing a first impurity of a second conductivity type in the semiconductor substrate through the first dielectric layer; (d) conducting a heat treatment to form a first well, and a second dielectric layer on the exposed surface of the semiconductor substrate in the first opening section; (e) forming a second mask layer having a second opening section on the first mask layer; and (f) forming a second well within the first well by introducing a second impurity of the first conductivity type in the semiconductor substrate through the second dielectric layer.

Method for manufacturing semiconductor device

A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages in a common substrate. A method for manufacturing the semiconductor device includes: (a) forming a first well including an impurity of a second conductivity type in a specified region of a semiconductor substrate of a first conductivity type; (b) forming a first impurity layer in a specified region of the first well by introducing an impurity of the first conductivity type by ion implantation; (c) forming a second impurity layer in a specified region of a semiconductor layer of the first conductivity type by introducing an impurity of the second conductivity type by ion implantation; and (d) diffusing impurities of the first impurity layer and the second impurity layer by a heat treatment to form a second well of the first conductivity type in the first well, and forming well-shaped offset layers of a source/drain layer of the second conductivity type.

A method is provided for manufacturing a semiconductor device that can secure a high breakdown voltage and yet optimize wells. The semiconductor device includes a semiconductor substrate of a first conductivity type, a well of the first conductivity type, a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a source/drain layer of the second conductivity type formed in the semiconductor substrate. The well of the first conductivity type includes a channel region and is formed in a manner not to overlap the source/drain layers.

Semiconductor device and its manufacturing method

A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages in a common substrate. The method includes: (a) introducing an impurity of a second conductivity type in a specified region of a semiconductor substrate of a first conductivity type to form a first impurity layer and a second impurity layer; (b) further introducing an impurity of the second conductivity type in a region of the second impurity layer to form a third impurity layer; and (c) conducting a heat treatment to diffuse impurities of the first impurity layer and the third impurity layer to form a first well of the second conductivity type and a second well of the second conductivity type having an impurity concentration higher than the first well.

Method for manufacturing semiconductor device that includes well formation

A semiconductor device, having a high breakdown voltage transistor and a low breakdown voltage transistor in a common substrate with different driving voltages, includes a semiconductor substrate of a first conductivity type, a first triple well formed in the semiconductor substrate and having a first well of a second conductivity type and a second well of the first conductivity type formed within the first well, a second triple well formed in the semiconductor substrate and having a third well of the second conductivity type and a fourth well of the first conductivity type formed within the third well, a low breakdown voltage transistor of the second conductivity type formed at the second well, and a high breakdown voltage transistor of the second conductivity type formed at the fourth well. The first well of the first triple well can have an impurity concentration higher than an impurity concentration of the third well of the second triple well.

Growing community of inventors

Sakata, Japan

Masahiro Hayashi