Ablic Inc.

Masahiro Hatakenaka

Mitsuhiro Yoshimura

Hideo Yoshino

In the semiconductor device, a high-concentration diffusion layer and a low-concentration diffusion layer are disposed around a drain diffusion layer of an ESD protection element. The high-concentration diffusion layer is separated from a gate electrode, and a medium concentration LDD diffusion layer is disposed in a separation gap. Variations in characteristics are suppressed by reducing thermal treatment on the high-concentration diffusion layer and a medium concentration diffusion layer.

Semiconductor device and semiconductor device manufacturing method

A semiconductor device having a first surface formed at a first height and a second surface formed at a second height on a semiconductor substrate includes: a base region formed in the semiconductor substrate; a trench formed from the first surface and the second surface into the semiconductor substrate; a gate insulating film covering an inner side of the trench; a gate electrode embedded to a third height; an insulating film formed on the gate electrode; a first region which has the first surface and in which a base contact region is formed; and a second region which has the second surface and in which a source region is formed, the first region and the second region being alternately arranged in the trench extension direction to prevent a reduction in channel formation density.

Vertical MOSFET having insulated trenches and base region contact

A semiconductor device in which a trench in a cell outer peripheral region configured to pull out a gate electrode and a trench in a cell region having a vertical transistor are formed with the same width to enable a reduction in chip area, and a manufacturing method thereof in which a gate contact hole is formed directly on a trench in a cell outer peripheral region on a self-alignment basis, and a gate wiring electrode is connected thereto are provided.

Semiconductor device and manufacturing method thereof

To obtain a semiconductor device in which a reduction in channel formation density in a trench extending direction is suppressed, provided is a semiconductor device including a first region and a second region alternately arranged in the trench extending direction. The first region includes a first front surface semiconductor electrode layer of a first conductivity type having a portion along an outer side surface of the trench from the front surface of the semiconductor device to the first height to which a gate electrode is embedded into the trench. The second region includes a base contact region having a depth from the front surface of the semiconductor device to the second height higher than the first height and a second front surface semiconductor electrode layer of the first conductivity type from the first height to the second height.

Semiconductor device having a gate electrode embedded in a trench

A reference voltage generator is constructed to be equipped with a first constant current circuit which outputs a first constant current with respect to an input voltage, a second constant current circuit which outputs a second constant current, and a voltage generation circuit which generates a voltage based on an input current, and to take a current based on the first constant current and the second constant current as an input current of the voltage generation circuit and output a reference voltage from the voltage generation circuit.

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Chiba, Japan

Masahiro Hatakenaka