Fujitsu Corporation

Inter-university Research Institute Corporation Research Organization of Information and Systems

Masahiro Goshima

Yi Ge

An instruction processing apparatus including a processor configured to execute a process including issuing, by an instruction scheduler, instructions that can be executed; holding, by a register file, data used by the instructions; executing, by an execution unit including a plurality of stages, the instructions issued by the instruction scheduler; detecting, by a detector, early termination in which an execution result of an intermediate stage, which is before a final stage among the plurality of stages, is the same as an execution result of the execution unit; and transferring, by a bypass controller, the data output from the register file or the execution result from the execution unit, to an input of the execution unit, and in response to the detector detecting the early termination, bypassing the execution result of the intermediate stage to the input of the execution unit.

Instruction processing apparatus and instruction processing method

A processor includes a queue configured to hold a memory access instruction including one or more addresses, a contracted address generator configured to generate a contracted address by contracting bits of multiple addresses in a case where the memory access instruction includes the multiple addresses, a conflict detector configured to detect a conflict between the contracted address and the address held in the queue, and an access controller configured to control processes of the memory access instruction held in the queue, based on a detection result of the conflict detector.

Processor and processing method

A processor includes request issuing units issuing an access request to a storage, a data array including banks holding sub data divided from data read from the storage based on the access request, a switch to transfer the access request to one of the banks, and first and second determination units. The first determination unit determines a cache hit when a tag address included in the access address matches a tag address held therein in correspondence with an index address included in the access address. The second determination unit determines a cache hit when identification information corresponding to a first tag address included in the access address and a second tag address included in the access address, match identification information and second tag address held therein. A cache controller makes access to the data array or storage, based on a determination result of the first or second determination unit.

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Chiyoda, Japan

Masahiro Goshima