Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Masahiro Gion

Masato Maede

Shiro Usami

Naoki Nojiri

Masaya Hirose

Daisuke Matsuoka

Kazuyuki Nakanishi

Katsuji Aoki

Hidetoshi Nishimura

Heiji Ikoma

Masaki Toyokura

Akihiko Ohtani

Akio Hirata

Kinya Daio

Atsushi Ubukata

Yoshifumi Matsumoto

Hisato Yoshida

Hisaki Watanabe

Akira Sota

Shinji Kinuyama

A semiconductor integrated circuit includes a power supply switch circuit which uses a PMOS transistor and an NMOS transistor to select a first power supply voltage applied to a first power supply input terminal or a second power supply voltage applied to a second power supply input terminal, and output the selected voltage as a power supply voltage to a third power supply output terminal, a first switch control circuit connected to the gate of the PMOS transistor, and a second switch control circuit connected to the gate of the NMOS transistor.

Semiconductor integrated circuit

In a level shift circuit allows satisfactory operation with short delay time in the case of low-voltage setting of a low-voltage source, for example, when a state of an input signal IN transitions from a H (VDD) level to a L level, a node Wprecharged to a H (VDD) level is discharged to ground (VSS) by a discharge circuit N, and decreases in potential. The decrease in potential propagates to a latch circuit LA, and an output of the latch circuit LA propagates to an output circuit OC. Further, an inversion signal of the node Wis input to the output circuit OC by bypassing the latch circuit LA. Thus, the output circuit OC starts operating prior to operation based on an output of the latch circuit LA.

Level shift circuit

A semiconductor integrated circuit includes a level shift circuit which is located so that a second IO cell region is interposed between the level shift circuit and a first IO cell region, and converts a signal output from an IO cell of the first IO cell region into a signal having an amplitude of a second voltage and outputs the resultant signal, and an internal circuit which is operated using the signal having the amplitude of the second voltage output from the level shift circuit. A signal interconnect via which the signal output from the IO cell of the first IO cell region is input to the level shift circuit is provided between the IO cell of the first IO cell region and the level shift circuit, extending over or in an IO cell of the second IO cell region.

In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes Wand Wexceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes Wand Wvia parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N, Nand two N-type low-voltage transistors N, Nfor receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.

There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuithas a control signal terminal INCNT, a first power imputer terminal IG, and a second power supply terminal IGas input terminals and has a first output terminal OGand a second output terminal OGas output terminals. The gate of a second P-type transistor Pis connected to the first output terminal OGof the gate control circuitand the gate of a second P-type transistor Pis connected to the second output terminal OGof the gate control circuit, wherein the first P-type transistor Pand the second P-type transistor Pare connected in series between a first power source VDDand a second power source VDDto form a switch section.

Power switching circuit

In a level shift circuit, for example, when an input signal IN changes from the L level to the H level, an N-type signal input transistor is made conducting and current flows in the N-type transistor. Accordingly, a first current mirror circuit amplifies the current flowing in the N-type transistor by predetermined number of times, increases the current driving capability for an inverted output node, and changes the inverted output node quickly to the L level. With the change to the L level of the inverted output node, an output node changes to the H level, a P-type transistor (first current interrupting circuit) is made non-conducting by the change, and the current fed from the first current mirror circuit is interrupted. Therefore, even when the power source voltage for the input signal and the inverted input signal is lowered, the operation is performed at high speed.

In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced. In FIG.an output signal of an inverter circuit INVconstituting a latch circuitconnected to the output terminal of an input sectionis used as an input signal of a control sectionThus, a control signal output from the control sectionto the input sectionis stabilized, thereby suppressing unnecessary operation of circuit elements and reducing unnecessary power consumption. In addition, the configuration of the control sectionis simplified. As a result, the number of transistors constituting the circuit and the circuit area can be reduced.

Flip-flop circuit

In a CMOS level shifting circuit including N-channel transistors that have sources to which a digital signal is supplied, a bias voltage Vref is supplied to gates of the N-channel transistors, and the bias voltage Vref is set to be higher than a high level voltage of the digital signal and lower than a value obtained by adding a threshold voltage of the N-channel transistors to the high level voltage of the digital signal. Thus, a level shifting circuit is provided that is capable of outputting a signal having subjected to stable level conversion, even when a voltage level of a low voltage signal is lowered.

Level shifting circuit

In a level shift circuit according to the invention, either an input signal IN or an inverted input signal XIN, which are input into the gate electrodes of n-type transistors for signal input, is also given to the substrate of that n-type transistor via p-type transistors for substrate bias. When the signal IN or XIN rises and changes, the threshold voltages of the n-type transistors for signal input is lowered due to the substrate bias effect. Consequently, even if the signal IN or XIN has a low voltage level, operation is carried out at high speeds. Also, when either an output signal OUT or an inverted output signal XOUT is changed to a high voltage level, the transistors for substrate bias become non-conducting, and thus the input signal IN or the inverted input signal XIN is not supplied to the substrate of the n-type transistors for signal input other than when the signal is changing. Consequently, a constant passing-through current does not flow to the substrate of these transistors.

An anlog boundary scan compliant integrated circuit system carries out a test more reliably and cuts down on power dissipated during normal operation. To perform a test of whether or not an interconnect is connected normally between integrated circuits, multiple logic circuits with mutually different input threshold voltages are provided to detect the logical level of a potential at a terminal, thereby improving the reliability of the test. Potential fixers and power isolators are optionally provided. During normal operation, the power fixers fix the output potentials of the logic circuits, while the power isolators electrically isolate the logic circuits from the ground. As a result, no current flows through the logic circuits or other circuits in succeeding stages while no tests are carried out.

Analog boundary scan compliant integrated circuit system

There is provided a correlation degree operation apparatus in which the search area is readily extensible, in which a high-speed process can be assured even though the search area is extended, and which can be formed in a simple arrangement. The search area memory stores the picture element data of a search area including ((m.times.M).times.L) candidate blocks. The correlation degree operation unit executes an operation of a degree of correlation between a reference picture block and each of the candidate blocks, with the use of picture element data supplied from the search area memory, this operation being executed by a pipeline process for each candidate block group composed of (M.times.L) candidate blocks. The search area memory has the function of supplying four picture element data at the same clock cycle. This enables the correlation degree operation unit to continuously execute the pipeline processes for the candidate block groups. It is therefore possible to continuously execute the operations of correlation degree between the reference picture block having (M.times.N) picture elements and ((m.times.M).times.L) candidate blocks.

Correlation degree operation apparatus, parallel correlation degree

A subtracter performs a subtraction (Xi-Yi) per corresponding components of two pairs of N-dimensional vector data (X1, X2, . . . XN), (Y1, Y2, . . . , YN). An exclusive disjunction circuit selects (Xi-Yi) when a result of subtraction is positive, and inverts bits of the result of subtraction to select the bit-inverted data (Xi-Yi) when the result of subtraction is negative. The selection is carried out using a most significant bit of the result of subtraction as a control signal. An accumulator accumulates the selected data and a value of the most significant bit of the result of subtraction. Accordingly only one subtracter suffice. Since the operation of adding 1 to the inverted data of the result of subtraction when the result of subtraction is negative is carried out concurrently with the accumulation of the result of subtraction by the accumulator, a vector correlation detecting circuit with less element and reduced operation time is contemplated.

Growing community of inventors

Kyoto, Japan

Masahiro Gion