Matsushita Electric Industrial Co., Ltd.

Kokuyo Co., Ltd.

Masahiro Fukui

Masakazu Tanaka

Noriko Shinomiya

Toshiro Akino

Shuji Tsukiyama

Yoshiyuki Kawakami

Shiro Dosho

Toru Iwata

Shiro Sakiyama

Mizuki Segawa

Takefumi Yoshikawa

Masahiko Toyonaga

Michikazu Matsumoto

Naoshi Yanagisawa

Yoshinori Takeuchi

Masaomi Toyama

Naoki Hayashi

Masaharu Imai

Keijiro Umehara

Ryoichi Suzuki

Chie Iwasaki

Yoko Iida

Koji Hamawaki

Ichiro Shigemoto

Takahiro Shiohara

Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Delay distribution calculation method, circuit evaluation method and false path extraction method

Chair

The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means () for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element () included in the first filtering means () for allowing a first current to flow in accordance with the first voltage; current generating means () for generating a second current at a given rate to the first current; second filtering means () for accepting, as an input, the second current and outputting a second voltage; and adding means () for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit

A physical design method optimizes the performance of an integrated circuit much more efficiently. After an initial layout is obtained for an integrated circuit, a set of process steps, including evaluating the overall performance of the integrated circuit, selecting a candidate cell and changing the performance of the cell, is carried out a number of times. In the step of selecting a candidate cell, a cell, which should have its performance changed, is selected from multiple cells included in the integrated circuit based on the performance evaluation result obtained. Then, by reference to a library, a characteristic representing the performance of the candidate cell is determined in accordance with an external condition imposed thereon.

Method of physical design for integrated circuit

In placement of 6-bit interconnection lines in parallel, for example, interconnection lines for three lower-order bits having a high signal change frequency and interconnection lines for three higher-order bits having a low signal change frequency are placed alternately, so that each interconnection line for a lower-order bit is sandwiched by interconnection lines for higher-order bits. With this layout, the interconnection lines for higher-order bits serve like shield lines for the interconnection lines for lower-order bits. This effectively suppresses increase in delay in signal propagation due to change of a signal propagating through an interconnection line for a lower-order bit and a signal propagating through an interconnection line for a higher-order bit to opposite phases, without increasing the area.

Wiring method in layout design of semiconductor integrated circuit, semiconductor integrated circuit and functional macro

In an automatic routing/designing process of an LSI using a maze algorithm, multiple sub-regions, formed by getting a grid column partitioned by a component placed in a routing region, are extracted. And grid point availability, representing the number of grid points available for routing, is obtained for each of these sub-regions. Also, if there is any open net, then the component is vertically moved upward by one grid unit, for example, to make the net routable. If the grid point availability of a sub-region, used for routing another net, has become negative as a result of the movement of the component, then the net is rerouted to pass other sub-regions. Accordingly, even if a height constraint, for example, has been imposed on the routing region, all of the nets can be routed successfully with the constraint satisfied without increasing the number of grid points in the column direction. As a result, the number of open nets can be minimized and all of the nets are much more likely to be routed successfully.

Routing path finding method for automated routing/designing process and computer-readable storage medium having stored thereon routing path finding program

There is no conventional method for precisely estimating under what external conditions each partial circuit, such as a library cell, is utilized in an actual integrated circuit at the time of designing the partial circuit. Therefore, by estimating the external conditions of a partial circuit when used in an integrated circuit so that the partial circuit is designed in accordance with the external conditions, the partial circuit having optimal performance for the external conditions can be designed. The step of external condition estimation can be formed so as to include the technology conversion step which technologically converts the layout for external condition extraction, that is prepared in advance, based on the technology information of an integrated circuit, which is the design objective; the layout extraction step of extracting layout extraction information which is external information influencing the operation of the partial circuit from the layout for external condition extraction that has been technologically converted; and the external condition calculation step of calculating external conditions of the partial circuit from the layout extraction information. In addition, by simply replacing the designed partial circuit with a partial circuit of a circuit for evaluation, the evaluation of the designed partial circuit can be easily carried out.

Method for design of partial circuit

A layout structure and a method for generating a layout for an integrated circuit more efficiently to catch up with remarkable developments of fabrication technologies of today. In generating a layout for a CMOS circuit, a pair of p- and n-channel transistors is used as a layout unit if one of these transistors is the dual of the other. These two transistors of are placed closely to each other so that when wires are connected to the source or drain of the p-channel transistor and to the source or drain of the n-channel transistor, those wires can be extended substantially vertically to each other.

Layout structure for integrated circuit, method and system for generating layout for CMOS circuit

In designing an integrated circuit, the size of a transistor is optimized together with the folding number thereof. The optimization of the size and folding number of the transistor is accomplished by using a folding model in which a plurality of folding numbers are assumed for one transistor size. In the folding model, if the lower limit value of the transistor size W is W and the height of a placement region for the transistor is H , the folding number N can be determined arbitrarily so long as W/H N&lE;W/W is satisfied. If the size of the transistor is optimized together with the folding number thereof by using the folding model so long as a given design constraint is satisfied, there can be designed an integrated circuit which has been improved in terms of area and performance.

Method and apparatus for transistor optimization, method and apparatus for layout design of integrated circuit, and integrated circuit

The present invention realizes the optimization of a transistor size with higher precision and in a shorter time, in designing a layout for an integrated circuit. A diffusion sharing estimation section estimates a diffusion-sharing region in the layout of the integrated circuit based on circuit data. A circuit characteristic evaluation section evaluates the characteristics, such as area, delay and power consumption, of the integrated circuit in accordance with the information about the diffusion-sharing region estimated by the diffusion sharing estimation section. A transistor size optimization section sets various size candidates for each of the transistors, which constitute the integrated circuit, provides these size candidates to the diffusion sharing estimation section and the circuit characteristic evaluation section, and then selects an optimum transistor size from the transistor size candidates thus set in accordance with the evaluation results obtained by the circuit characteristic evaluation section. Thus, a transistor size can be determined while taking the diffusion sharing into consideration. In addition, unlike a conventional method, it is no longer necessary to repeatedly re-determine a transistor size and perform a compaction.

Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method

Method and apparatus for suppressing change in wiring delay time resulting from cell interchange and thereby satisfying required specifications in a short period of time with certainty during LSI layout designing. Cells are arranged in parallel to each other and routed based on circuit designing information, thereby designing a block layout including a plurality of cell rows. A cell not satisfying the required specifications is extracted from the block layout, and a level of drivability required for the cell to satisfy the required specifications is calculated. The extracted cell in question is interchanged with a substitute cell. The substitute cell has equivalent logic, a required level of drivability and the same width and terminal position in the cell arrangement direction reaction a cell row as the counterparts of the cell in question and is provided in a stretchable cell library.

Method and apparatus for designing LSI layout, cell library for designing LSI layout and semiconductor integrated circuit

First, initial routing is performed on a net. If a design rule error exists in a wire already routed as a result of the initial routing, the wire already routed, causing the design rule error, is removed. Next, if the wire already routed and removed is a wire interconnecting a movable terminal, freely placeable within a predetermined region, to another terminal, then the movable terminal is displaced within the predetermined region and the removed wire is re-routed such that the displaced movable terminal is interconnected to the other terminal. Accordingly, the movable terminal can be located at an appropriate position within the predetermined region in accordance with the situation of surrounding wires. As a result, routing results of a higher density can be obtained.

Automatic routing method

The invention provides a functional module model for realizing optimal pipelining. The functional module model includes division line data representing division lines corresponding to positions where pipeline registers can be inserted and delay/area data representing the trade-off relationship between the delay and the area of each division area partitioned by the division lines. By using this functional module model, a pipeline register insertion position is selected among the division lines represented by the division line data, and the delay and the area of each division area are set on the basis of the trade-off relationship represented by the delay/area data. Thus, a pipelined circuit with a minimized area can be synthesized.

Functional module model, pipelined circuit synthesis and pipelined circuit device

An equivalent circuit converter reads out transistor-level circuit diagram data and equivalency conversion rule data, converts circuit data based on the equivalency conversion rule data, and then feeds back the converted circuit data to the circuit diagram data. An estimate calculator reads out the circuit diagram data, which has been converted by the equivalent circuit converter, and environmental variable data, thereby calculating an estimate representing a degree of optimization. In response to the estimates supplied from the estimate calculator, a circuit optimizer selects partial circuits to be subjected to equivalent circuit conversion during the optimization of the circuit. Then, the circuit optimizer sequentially determines whether or not each of the partial circuits should be converted into an associated equivalent circuit, thereby optimizing the entire circuit.

Growing community of inventors

Osaka, Japan

Masahiro Fukui