Fujitsu Corporation

Fujitsu Semiconductor Limited

Masahiko Toichi

Tomonori Kubota

Yasuyuki Murata

Hiroshi Hatano

Takashi Nishikawa

An apparatus sequentially acquires, from a plurality of reference imaging devices for imaging a silhouette imaged with a base imaging device from viewpoints different from a viewpoint of the base imaging device, silhouette existing position information based on the reference imaging devices, and transforms the silhouette existing position information into a common coordinate system, where the silhouette existing position information indicates an existing position of the silhouette. The apparatus detects a silhouette absence range in which the silhouette does not exist, based on a result of comparison of the silhouette existing position information acquired this time and the silhouette existing position information acquired last time, and searches a range in which the silhouette exists, based on the silhouette absence range.

Effective search for a silhouette cone to reconstruct a three dimensional shape of an object

A processor controls a reconfigurable circuit capable of dynamically reconfiguring a circuit which achieves a task of a computer, the processor executes a process having determining, when reconfiguring each of circuits which achieve a plurality of tasks in the reconfigurable circuit, assigned times of time sharing of the plurality of tasks or priority processing ranks of the plurality of tasks based on costs needed in the reconfigurable circuit for respective circuits which achieve the plurality of tasks.

Processor for changing weight of costs needed in reconfigurable circuit

A calculation device includes a programmable logic device including a plurality of circuit arrangement areas each to which power supply voltage allowed to be independently controlled is supplied and a calculation circuit coupled to the programmable logic device. The calculation circuit arranges a main circuit that executes specific processing in a first circuit arrangement area included in the plurality of circuit arrangement areas, acquires a second circuit arrangement area in which a sub circuit that executes the specific processing is allowed to be arranged, included in the plurality of circuit arrangement areas and in which the main circuit is not arranged, arranges the sub circuit in the second circuit arrangement area, and causes one of the main circuit and the sub circuit to execute the specific processing.

Calculation device and calculation method

A memory controller includes: a first generating unit that generates a read-address to read a data element sequence having a plurality of data elements from a bank of a memory; a second generating unit that generates a position signal indicating a position of a data element to be selected from the data element sequence, and an order signal indicating a storing order for storing the data element to be selected into a register; and a selector unit that selects, according to the position signal, the data element to be selected from the data element sequence read out from each of the plurality of the banks, and stores the selected data element in the storing order indicated by the order signal into the register, wherein the data element stored in the register is processed in the storing order by a vector processor.

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Urayasu, Japan

Masahiko Toichi