Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Panasonic Corporation

Tower Semiconductor Ltd.

Tower Partners Semiconductor Co., Ltd.

Masahiko Sakagami

Hiroshige Hirano

Shunichi Iwanari

Yasuo Murakuki

Kunisato Yamaoka

Takashi Miki

Yasushi Gohou

Tetsuji Nakakuma

Hideki Kawai

Yakov Roizin

Erez Sarig

Micha Gutman

Hiroaki Kuriyama

Masaru Fujii

Kiyoto Ohta

Akihiro Yamamoto

Yoshikazu Maeyama

Toshitaka Uchikoba

A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.

Semiconductor device for writing to a storage element

Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory corestarts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cellin the memory corecorresponding to the received external address signal ADD is selected. When a data read-out from the memory cellor a data write-in to the memory cellis complete, a rewrite timeris activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell

Semiconductor memory device

In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

Semiconductor memory device having a bitline amplified to a positive voltage and a negative voltage

A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Ferroelectric memory and method for reading data from the ferroelectric memory

Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory corestarts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell, in the memory core, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cellor a data write-in to the memory cellis complete, a rewrite timeris activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell

To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage areaformed from electrically-rewritable nonvolatile memory and a second setting function storage areaformed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address registerand transfer of operation mode setting information to an operation mode registerare selectively performed.

Semiconductor storage device

A semiconductor memory device having a semiconductor substrate includes a plurality of reference cellsand a plurality of bit lines. The reference cellsare formed in a region near the centerline of a predetermined region of the semiconductor substrate which is perpendicular to the bit lines. The bit linesform pairs each composed of two adjacent bit lines. Two bit linesin each pair have a first parallel state and a second parallel state in which positions of the two bit lines are reversed from the first parallel state. Each pair of bit lineshas at least one cross sectionwhere one of the pair of bit linescrosses the other, to switch between the first parallel state and the second parallel state. The cross sectionis provided in the predetermined region of the semiconductor substrate such that the length of a bit linein the first parallel state is equal to the length of the bit linein the second parallel state. The semiconductor memory device is reduced in size.

A semiconductor memory apparatus including a simple circuit configuration and is capable of randomly accessing fuse data. A fuse cellincluding a fuseis connected to a pair of bit lines of a memory circuit. The fuseand a fuse data output circuit (which includes a resistorand an inverter) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch. By allowing a column decoderfor selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.

Semiconductor memory apparatus

In a semiconductor substrate of a first conductivity type, first and second high-concentration layers of a second conductivity type are formed in spaced relation to each other. A reference voltage is applied to the second high-concentration layer. A conductive layer provides an electrical connection between the first high-concentration layer and an input pad for inputting an input signal to an input circuit or input/output circuit. A first low-concentration layer of the second conductivity type is formed in the region of the semiconductor substrate immediately underlying the first high-concentration layer.

Semiconductor device

A memory control device for controlling a random access memory provides with an arbiter for generating write start and read start signals in response to WRITE and READ commands which are obtained by frequency-dividing writing and reading clock signals, respectively and a memory control circuit comprised of first and second delay circuits for delaying the write start and read start signals by predetermined times, respectively, and first and second RS flip-flop circuits for generating write and read control signals in response to the write start and read start signals, respectively, which are reset by reset signals output from the first and second delay circuits, respectively.

Memory control device

A dynamic type semiconductor memory in which a bit line is made to be connected to an electric potential different from a precharge potential after a precharge of the bit line is effected and one of word lines is selected and before a sensing amplifier operates. Thereby, all data stored in memory cells of the same row address can be cleared or preset in a cycle. Further, data stored in all of memory cells of which the number is equal to that of row addresses multiplied by that of column addresses can be cleared or preset in cycles of which the number is equal to that of the row addresses. Consequently, a clearance of contents of or a presetting of all memory cells can be effected at a high speed.

Dynamic type semiconductor memory

A semiconductor device contains circuits composed on a semiconductor substrate which are divided at least into two circuit blocks as seen from the aspect of supplying electrical power, and the pad and wiring for feeding a supply potential and/or grounding potential to the first circuit block, and the pad and wiring for feeding the supply potential and/or grounding potential to the second circuit block other than the first circuit block are electrically independent of each other. In this constitution, it is possible to prevent malfunctions of the second circuit block and distortions of the output signal due to fluctuations of the supply potential or grounding potential occurring during operation of the first circuit block. It is also possible to prevent malfunctions of the first circuit block and distortions of the signal on the first circuit block due to fluctuations of the supply potential or grounding potential occurring due to a malfunction of the second circuit block.

Semiconductor device having multiple supply potential paths for reducing

This invention is realized, in sum, by providing at least one reset input terminal, aside from a reset input terminal to which a request end signal is supplied, to output stage RS flip-flops of plural latch circuits to which plural request signals are supplied respectively. The signal of a first output terminal of the output stage RS flip-flop of a specified latch circuit of the plural latch circuits is supplied to a reset input terminal of the output stage RS flip-flop of the other latch circuit and a delay circuit is connected between a second output terminal and the other reset input terminal of the output stage RS flip-flops of each latch circuit. Accordingly, if plural request signals are supplied at substantially the same time, the competition of these request signals may be settled. Besides, by setting the delay time of each delay circuit longer than the time required from the supply of the signal to the set input terminal of the corresponding output stage RS flip-flop until the signal is latched in the output terminal, even if pulsive signals are supplied to the output stage RS flip-flops, oscillation of the output stage RS flip-flops may be prevented.

Arbiter circuit using plural-reset RS flip-flops

In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input terminal, and other succeeding stages are sequentially and straightly located at intervals; the chain of the stages is folded at a particular stage, and further succeeding stages are sequentially and straightly located at intervals so as to fill in the spaces between the other stages, thus, the unbalance of the load capacitance between said stages and the functional unbalance between the shift registers can be minimized.

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Kyoto, Japan

Masahiko Sakagami