Panasonic Corporation

Masahiko Sagisaka

Taiji Akizuki

Hisashi Adachi

Tomoaki Maeda

Yusaku Tada

Masatoshi Matsushita

Yoichiro Horiuchi

This receiving apparatus achieves circuit size reduction and consumption power reduction, while still having an advantage of high-speed processing. In a receiving apparatus (), a frequency component detector () has a Fourier conversion operation unit provided therein, and performs high-speed Fourier conversion with respect to digital signals outputted from an ADC (), said high-speed Fourier conversion being performed within a range instructed by means of an operation range control unit (), and the frequency component detector detects a plurality of frequency components (FFT signals) of the digital signals. The operation range control unit () sets, using the FFT signals outputted from the frequency component detector (), the frequency range within which the Fourier conversion operation is to be performed, and instructs the range to the frequency component detector ().

Receiving apparatus and demodulation method

A receiver simultaneously receives a plurality of signals on a plurality of channels, which have been modulated using frequency shift keying (FSK). A calculation range controller detects a Mark frequency and a Space frequency for each channel, determines for each channel a frequency range for Fourier transform calculation of the plurality of receiving signals, based on the detected Mark frequency and the detected Space frequency and indicates the frequency range to a frequency component detector. The frequency component detector performs Fourier transformation on the determined frequency range for each channel and detects, for each channel, frequency components (FFT signals) of the plurality of receiving signals respectively. The channel shifter allocates the FFT signals output from the frequency component detector to data of channelto channel N and outputs the signals to respective demodulators.

A frequency range for Fourier transform is controlled and a digital signal is subjected to fast Fourier transform within the controlled range, whereby a plurality of frequency components (FFT signals) in the digital signal are detected. A transmission rate of a received signal is determined using the detected FFT signals and the FFT signals are demodulated by an operation at a speed corresponding to the determined transmission rate.

A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.

Clock signal generation apparatus

A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Delta sigma A/D modulator

A modulator, and more particularly an HPSK modulator, is disclosed that enables the circuit scale to be reduced and also enables power consumption to be reduced. An HPSK modulatorincorporated in a radio communication apparatus or the like is equipped with a spreading code multiplication section, a complex arithmetic section, a coefficient determination section, and raised COS filtersand. Spreading code multiplication sectionmultiplies transmit data DPDCHby a spreading code Cd. Complex arithmetic sectionperforms complex arithmetic on an output signal output from spreading code multiplication sectionand a scrambling code Sn, and performs conversion to complex data. Coefficient determination sectiondetermines a filter coefficient Adbased on a gain factor &#x3b2;dthat determines transmission power. Raised COS filtersandband-limit the complex data using the filter coefficient.

Modulator

In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.

Delta-sigma modulator and DA converter apparatus including delta-sigma modulator changing order of filter

An A/D converter that supports multi-mode and that can minimize power consumption is provided. A hybrid A/D converter comprises: hybrid stages composed of 1.5-bit A/D converter for pipeline use that convert analogue input signals into digital signals; 1/1.5-bit D/A converters that switch between pipeline use and delta-sigma modulation use according to the mode in use; analogue adders that subtract output of the 1/1.5 D/A converters from the analogue input signals; and analogue operation circuits that receive as input the output of the analogue adders and function as amplifiers in pipeline mode and as integrators in delta-sigma mode.

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Kyoto, Japan

Masahiko Sagisaka