Kabushiki Kaisha Toshiba

Ricoh Company, Ltd.

Toshiba Memory Corporation

Kioxia Corporation

Nec Corporation

Other

Skhynix Inc.

National Institute of Advanced Industrial Science and Technology

Masahiko Nakayama

Tadashi Kai

Hiroaki Yoda

Tatsuya Kishi

Toshihiko Nagase

Sumio Ikegawa

Hisanori Aikawa

Masatoshi Yoshikawa

Eiji Kitagawa

Masaru Toko

Yoshiaki Fukuzumi

Daisuke Watanabe

Naoharu Shimomura

Jyunichi Ozeki

Makoto Nagamine

Yutaka Hashimoto

Katsuya Nishiyama

Kazumasa Sunouchi

Minoru Amano

Kazuya Sawada

Hiroshi Akiyama

Akiyuki Murayama

Tsuneo Inaba

Tadaomi Daibou

Keiji Hosotani

Hiroshi Koide

Koji Ueda

Shinji Yuasa

Akihiko Shimizu

Youngmin Eeh

Yasuyuki Sonoda

Choon Kun Ryu

Hyung Suk Lee

Jae Geun Oh

Gaku Sudo

Hideyuki Sugiyama

Yoshihisa Iwata

Yoshiaki Saito

Tomoaki Inokuchi

Tomomasa Ueda

Takao Marukame

Hiroyuki Kanaya

Michiaki Shinotsuka

Katsuhiko Hoya

Mizue Ishikawa

Masayoshi Iwayama

Young Min Eeh

Koji Ando

Akio Fukushima

Kuniaki Sugiura

Hitoshi Kubota

Kiyoshi Yokomori

Satoshi Yanagi

Shigeto Fukatsu

Taro Nagahama

Hironobu Furuhashi

Shigeru Oohchida

Min Suk Lee

Keum Bum Lee

Soichi Oikawa

Shintaro Sakai

Kei Yakushiji

Nobuyuki Ogata

Sook Joo Kim

Hiroshi Goto

Masaki Kato

Kenji Tsuchida

Katsuyuki Yamada

Akihiro Nitayama

Hiroyoshi Sekiguchi

Shigeki Takahashi

Michiharu Abe

Hiroshi Watanabe

Masaru Shinkai

Katsuyuki Fujita

Eiko Hibino

Toshihiro Shigemori

Hiroshi Maegawa

Kenji Noma

Shigeyoshi Misawa

Satoshi Seto

Takao Ochiai

Kay Yakushiji

Kenji Yamauchi

Hiromi Noro

Shogo Itai

Rina Nomoto

Mikio Miyata

Tomomi Funayama

Masatoshi Yoshkawa

Haruhiko Kono

Kenji Fukuda

Ahmetserdar Demiray

Masashi Kawamura

Ji Hwan Hwang

According to one embodiment, a memory device includes a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a third memory cell adjacent to the first memory cell in a second direction, each of the first, second, and third memory cells including a resistance change memory element and a switching element. The switching element includes first and second electrodes, and a switching material layer between the first and second electrodes, the first and second electrodes overlap each other when viewed from the first direction, the first electrodes in the first and second memory cells are apart from each other, and the switching material layers in the first and second memory cells are continuously provided.

Memory device

A storage device includes a memory cell including a variable resistance element and a switching element having snapback current-voltage characteristics. The switching element includes a first conductive layer in contact with the variable resistance element, a second conductive layer, and a switching layer provided between the first conductive layer and the second conductive layer. The switching layer includes at least one switching member and a first insulating layer having a thermal conductivity higher than 1.4 W/m/K. A cross-sectional area of the switching member at a connection surface between the switching layer and the first conductive layer and a cross-sectional area of the switching member at a connection surface between the switching layer and the second conductive layer are each smaller than a cross-sectional area at a connection surface between the first conductive layer and the variable resistance element.

Storage device

A magnetic memory device including a first memory cell which includes a first stacked structure including a magnetic layer and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer. Each of the first stacked structure and the second stacked structure includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A concentration of iron (Fe) contained in the first magnetic layer included in the first stacked structure and a concentration of iron (Fe) contained in the first magnetic layer included in the second stacked structure are different from each other.

Magnetic memory device

According to one embodiment, a magnetic memory device includes a magnetoresistance effect element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a variable magnetization direction, a third magnetic layer having a fixed magnetization direction and a nonmagnetic layer, the first magnetic layer being provided between the second and third magnetic layers, and the nonmagnetic layer being provided between the first and third magnetic layers. The second magnetic layer has a superlattice structure in which first element layers and second element layers are alternately stacked. The first element is Co, and the second element is selected from Pt, Ni and Pd, and the second magnetic layer contains Cr as a third element.

A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

Nonvolatile storage device

A storage device includes a memory cell array in which a plurality of memory cells respectively including a variable resistance memory element are divided into a plurality of memory blocks, the plurality of memory cells including a first memory cell and a second memory cell that are in the same memory block, and a detection circuit. During a read operation in which the first memory cell is a read target, the detection circuit compares a first resistance value, which is a resistance value of the variable resistance memory element in the first memory cell, with a second resistance value, which is a resistance value of the variable resistance memory element in the second memory cell, and determines a value of data stored in the first memory cell based on whether or not the first resistance value is higher or lower than the second resistance value.

According to one embodiment, a storage device includes first wirings extending in a first direction and second wirings extending in a second direction. A memory cells are connected between the first wirings and the second wirings and include a variable resistance memory element. A first drive circuit is provided for supplying voltages to the first wirings, and a second drive circuit is provided for supplying voltages to the second wirings. The first drive circuit applies a first voltage to a selected first wiring, the second drive circuit applies a second voltage to a selected second wiring. A voltage between the second voltage and one-half of the sum of the first and second voltages is applied to a non-selected first wiring, and a voltage between the first voltage and one-half of the sum of the first and second voltages is applied to a non-selected second wiring.

According to one embodiment, a magnetic device includes a stacked body including a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first magnetic layer and the second magnetic layer. The stacked body has a quadrangular planar shape, the stacked body has a first side dimension in a first direction parallel to a surface of a substrate and a thickness in a second direction perpendicular to the surface of the substrate, and a ratio of the first side dimension to the thickness is in a range of 0.10 to 4.0.

Magnetic device and memory device

According to one embodiment, a magnetic memory device includes a first memory cell which includes a first stacked structure including a magnetic layer, and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer, wherein each of the first stacked structure and the second stacked structure has a structure in which a plurality of layers including a predetermined layer are stacked, and the predetermined layer included in the first stacked structure and the predetermined layer included in the second stacked structure have different thicknesses.

A nonvolatile storage device includes first and second interconnections and a memory cell between the first and second interconnections. The memory cell includes a storage element, a first switch, and a second switch. The first switch has two terminals and transitions from an off-state to an on-state when a first threshold voltage is applied between its terminals and then voltage between the terminals falls to a first hold voltage. The second switch has two terminals and transitions from an off-state to an on-state when a second threshold voltage is applied between its terminals and then voltage between the terminals falls to a second hold voltage. An off-current of the first switch is less than an off-current of the second switch. The first threshold voltage is greater than the second threshold voltage, which is greater than the first hold voltage, which is greater than or equal to the second hold voltage.

A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a current level of the second pulse is different from a current level of the first pulse.

Magnetoresistive memory device with different write pulse patterns

According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.

Semiconductor memory device

Growing community of inventors

Yokohama, Japan

Masahiko Nakayama