Kabushiki Kaisha Toshiba

Amphenol Fci Asia Pte. Ltd.

Amphenol Fci Connectors Singapore Pte. Ltd.

Masahiko Motoyama

Motomu Kajiura

Naotaka Sasame

Kenji Sakaue

Shinichi Kawamura

Atsushi Shimbo

Koichi Fujisaki

Hirofumi Muratani

Yasuro Shobatake

Yoshinari Kumaki

Yasutoshi Kameda

Fumihiko Sano

Kenji Ohkuma

Hanae Ikeda

Yuuki Tomoeda

Ryouichi Bandai

An electrical connector includes a housing, first and second sets of terminals and a spacer. The housing has a first sidewall, a second sidewall spaced apart from the first sidewall and a cavity between the first and second sidewalls. The first set of terminals is disposed in the cavity adjacent to the first sidewall. The second set of terminals is disposed in the cavity adjacent to the second sidewall. The spacer is disposed in the cavity between the first and second sets of terminals.

Electrical connector with cavity between terminals

A circuit board connector comprises a housing, at least one signal contact disposed in the housing, and a pair of locking arms attached to the housing. The housing has a slot formed therein, for receiving a circuit board. Each locking arm has a latch movably disposed in the slot. The pair of locking arms are resiliently deformable relative to the housing between a lock position at which the latch is positioned to block the slot, to lock a circuit board to the connect, and an unlock position at which the latch is positioned to form a clearance in the slot, to allow disconnection of the circuit board from the connector.

Circuit board connector having a pair of locking arms

A cryptographic module that performs a cryptographic operation is provided with: a register that retains first data related to key data to be used in the cryptographic operation; a register that retains second data without dependency on the first data; a selector that alternately selects and outputs the contents of the register retaining the first data and the register retaining the second data; and a left shift circuit that performs a predetermined shift operation on data outputted from the selector.

Cryptographic module and IC card

An encryption processing circuit includes: a decoder configured to convert a binary input data used for predetermined encryption computing into a first plurality of bit data of a constant hamming weight independently of a hamming weight of the input data; a wiring network configured to receive the first plurality of bit data converted by the decoder, the wiring network further configured, for the purpose of the predetermined encryption computing, to change a bit pattern of the received first plurality of bit data by replacing bit positions of the first plurality of bit data, and to generate a second plurality of bit data; and an encoder configured to convert the second plurality of bit data generated in the wiring network into a binary output data.

Encryption processing circuit and encryption processing method

A logic circuit that executes a prescribed arithmetic processing includes a decoder that converts one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of the input data, an interconnect network that is connected to the decoder, changes a bit pattern of the first plurality of bit data and generates a second plurality of bit data, according to receiving the first plurality of bit data converted according to the decoder, and substituting a bit position of the received first plurality of bit data for the purpose of the prescribed arithmetic operation, and an encoder connected to the interconnect network and converts the second plurality of bit data generated in the interconnect network into one or more binary output data.

Logic circuit

Expanded key schedule circuit for common key encryption system in which expanded keys are used in a predetermined order in data randomizing process for encryption and in a reversed order in data randomizing process for decryption, comprises round processing circuits connected in series. The round processing circuits subject the common key or sub key of a previous stage to a round function to output a sub key. The sub key of the last stage is equal to the common key. The expanded keys are generated from the sub keys.

Encryption apparatus, decryption apparatus, expanded key generating apparatus and method therefor, and recording medium

An encryption apparatus provided with a Feistel type encryption algorithm includes a function operation unit that operates a non-linear function, and changing unit configured to supply the function operation unit with random data unrelated to an encryption operation result. In this way, a countermeasure can be taken against a DPA attack following the end of an operation by the encryption operation apparatus provided with the Feistel type encryption algorithm.

Method and apparatus for encrypting data

There is provided a compact ATM switch. Each of the bit values of at least one of counters for counting the number of ATM cells in a cell buffer is set to be &ldquo;H&rdquo; when the at least one of counters is preset.

ATM switch

An ATM switch having multiple input and output ports is provided. The ATM switch receives ATM cells through the input ports and outputs the ATM cells through one of the output ports in accordance with output port information included in the ATM cells. An output buffer is also provided for each of the output ports to store ATM cells to be output through the output port. A cell counter is provided for each of the output buffers to count the number of ATM cells being stored in the output buffer. Additionally, the ATM switch includes counter verification circuitry for determining whether the cell counters are correctly counting the number of ATM cells stored in the output buffers. In one preferred embodiment, the counter verification circuitry includes a global cell counter that counts the total number of ATM cells being stored in all of the output buffers, an accumulator that determines the total number of ATM cells counted by the cell counters, and a comparator for comparing the accumulated count value with the global count value. Thus, the proper operation of the cell counters can be verified. This minimizes the possibility of improper operation due to a malfunction, even when the ATM switch is operated continuously for a long time period.

Asynchronous transfer mode switch including cell counter verification

A packet switch has a buffer memory for storing data obtained from data packets having routing tags input from a plurality of different input ports. Plural routing tag registers store the respective routing tags in the order of input. Plural address information registers respectively corresponding to the plural routing tag registers store address information representative of a buffer memory storage region where data corresponding to the routing tags are stored. A controller searches the routing tag registers in the order of their input. A reading is made of address information stored in the address information registers corresponding to routing tags for a special output port. Data stored in the storage region of the buffer memory indicated by the address information is output to the special output port. After the routing tag registers and the address information registers corresponding to the data have been output to the output port, contents of the routing tag registers and the address information registers are shifted to the next routing tag registers and address information registers in order.

Packet switch and buffer for storing and processing packets routing to

A unit cell switch includes a plurality of input communication routes and output communication routes for transferring data cells therebetween, a plurality of first conversion devices for converting each cell given from these input communication routes into a desired form, a plurality of second conversion devices for converting each data given from the first conversion devices into a suitable form and transferring the resultant data to one of these output communication routes. Cell storing devices respectively receive and temporarily store cells transferred from corresponding first conversion devices based on address information given to the cells. A control device holds and controls route and address information on cells to be stored in the cell storing devices as unitary data, and decides a write address of each cell storing device to which a cell is given from the corresponding first cell conversion device and a read address of each cell storing device from which a cell is outputted to a cell switch device based on the route and address information. A cell switch device introduces cells to desired second cell conversion devices from corresponding cell storing devices under control of the transfer control device.

Growing community of inventors

Kanagawa, Japan

Masahiko Motoyama