Seiko Epson Corporation

Masahiko Moriguchi

Satoru Ito

Junichi Karasawa

Takashi Kumagai

Satoru Kodaira

Kazuhiro Maekawa

Noboru Itomi

Hisanobu Ishiyama

Takashi Fujise

Shuji Kawaguchi

Takayuki Saiki

An integrated circuit device includes first to Nth circuit blocks CBto CBN, a first interface region disposed along a fourth side and on the Dside of the first to Nth circuit blocks CBto CBN, and a second interface region disposed along a second side and on the Dside of the first to Nth circuit blocks CBto CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction Dover the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.

Integrated circuit device and electronic instrument

An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TCand TC, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal, and a pad arrangement region in which data driver pads Pand Pfor electrically connecting the data lines and the output lines QLand QLof the data driver block are disposed. The control transistors TCand TCare disposed in the pad arrangement region.

A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.

An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.

In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

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Suwa, Japan

Masahiko Moriguchi