Kabushiki Kaisha Toshiba

Masahiko Chiba

Fujio Masuoka

Yoshihisa Iwata

Yasuo Itoh

Masaki Momodomi

Riichiro Shirota

Ryouhei Kirisawa

Koichi Toita

Tetsuo Endo

Hiroshi Iwahashi

Kazunori Ohuchi

Shigeyoshi Watanabe

Satoshi Inoue

Ryozo Nakayama

An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic 'one' e.g.) in the selected cell, by applying an 'H' level voltage to the bit line, applying an 'L' level voltage to a word line connected to the selected cell, applying the 'H' level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the 'L' level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

Non-volatile semiconductor memory with NAND cell structure and switching

An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an 'L' level voltage (approximately 0 V) to a word line connected to the selected cell, applying an 'H' level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the 'H' and 'L' level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic '0' data, the intermediate voltage is applied also to the specific bit line.

Electrically erasable programmable read-only memory with NAND cell

An electrically erasable programmable read-only memory has an array of programmable memory cells connected to parallel bit lines on a semiconductive substrate. The memory cells include NAND cell blocks each of which has a first selection transistor coupled to a corresponding bit line, a second selection transistor coupled to the ground potential, and a series array of memory cell transistors each having a floating gate and a control gate. Word lines are respectively connected to the control gates of the memory cell transistors. In a data read mode, a selection transistor of a certain NAND cell block including a selected memory cell transistor is rendered conductive to connect this cell block to a bit line associated therewith. Under such a condition, a low or 'L' level voltage is applied by a row decoder & bootstrap circuit section to a word line connected to the selected memory cell transistor, and a pulse voltage signal having a high or 'H' level is supplied by the row decoder & bootstrap circuit section to the remaining word lines, so that data stored in the selected memory cell is read out. The 'H' level of the voltage signal is higher than the power supply voltage and yet lower than a normal 'H' level used in data write and erase modes. The pulse width of the pulse voltage signal is shorter than the period of one read cycle.

Nonvolatile semiconductor memory device with NAND cell structure

An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an 'L' Level voltage (approximately O V) to a word line connected to the selected cell, applying an 'H' level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the 'H' and 'L' level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic '0' data, the intermediate voltage is applied also to the specific bit line.

Electrically erasable programmable read-only memory with NAND

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Aomori, Japan

Masahiko Chiba