Hitachi, Ltd.

Masahide Tsuboi

Takashi Moriyama

Koichi Okazawa

Masaya Umemura

Tetsuo Hiramitsu

Michinori Naitoh

Masumi Terao

Hiroshi Murashima

An information processing apparatus with a hierarchized bus structure having a system bus connected to central processing units and cache memories and an I/O bus connected to I/O devices. In response to a DMA request from the I/O device, a memory controller connected to both buses and to a main memory compares previous snoop addresses stored in a buffer memory of the memory controller with a current address contained in the DMA request to check whether the current DMA request is coincident with the past snoop process. If the comparison indicates a coincident snoop process, a snoop access process request is inhibited to be output to the system bus and cache memory. With this operation, the number of snoop accesses for DMAs to the same block of the cache memory can be reduced and a time during which the system bus is occupied can be shortened, to thereby improve the system performance.

Information processor with snoop suppressing function, memory controller, and direct memory access processing method

In an information processing system having a bus bridge connected between a plurality of buses for data transfer therebetween, the bus bridge is provided with a RAS data acquisition bus operating independently from the plurality of buses and a RAS data acquisition circuit for acquiring RAS data, the RAS data acquisition circuit acquires RAS data in the bus bridge or RAS data of a processor or an I/O device on a bus connected to the bus bridge, in response to a command supplied from an external circuit via the RAS data acquisition bus. The RAS data acquisition circuit sends the acquired RAS data to the external circuit via the RAS data acquisition bus.

Data processing system with RAS data acquisition function

Growing community of inventors

Owariasahi, Japan

Masahide Tsuboi