Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Masahide Nagumo

Tadashi Kojima

Jun Inagawa

Kunihiko Kodama

Hiromi Kusakabe

Meisei Nishikawa

An apparatus, a signal processing circuit and a method for reproducing data stored on a disc to prevent a buffer memory from going overflow/underflow. Writing information data read from the disc to the buffer memory is performed in synchronism with a reproduction stage clock signal, and reading from the buffer memory is in synchronism with a signal processing stage clock. The signal processing stage clock for reading information data from the buffer memory is changed in accordance with the amount of information data stored in the buffer memory for preventing interruptions in data reproduction.

Disc data reproducing apparatus and signal processing unit for

A control system for deinterleaving memories in a digital audio reproducing apparatus. A plurality of cross-interleaved symbols are written into or read out from the memory areas of a RAM. The control system includes three processors for controlling the symbols. The first processor prepares a memory area with a predetermined storage capacity in the RAM. The second processor reads and writes the first symbol of a plurality of cross-interleave symbols into the memory area. The third processor likewise reads and writes the second symbol into the memory area. The second processor includes a counter for determining the address. The third processor includes an adder producing a sum of the counter output and a fixed amount to determine the second address.

Control system for deinterleaving memories in digital audio reproducing

An error correction circuit in which an error location polynomial is determined on the basis of the code word of the code of a double correction BCH symbol in Galois field GF(2.sup.m), thereby determining the error location and error pattern necessary for the error correction. The error correction circuit includes: (a) means for generating a syndrome S.sub.i (i being an integer) from the code word: (b) first and second means for holding S.sub.1 and S.sub.0 out of the syndromes outputted from the syndrome generating means; (c) means for effecting the following calculation on the basis of the syndrome generated by the syndrome generating means:

Error correction circuit

An apparatus divides one element .alpha..sup.i of a Galois field GF(2.sup.m) by another element .alpha..sup.j of the field. Divider data .alpha..sup.j are supplied to one of the first linear shift registers and to the other first linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. Simultaneously, dividend data .alpha..sup.i are supplied to one of the second linear shift registers and to the other second linear shift registers through .alpha..sup.N1, .alpha..sup.N2, . . . multiplier circuits, respectively. '1' detector circuits are connected to the outputs of the first linear shift registers, respectively. The first linear shift registers and the second linear shift registers are shifted several times until any '1' detector circuit detects '1' in response to output signals from a 2-input AND gate. When '1' is detected, a NOR gate supplies a signal of logical '0' to the AND gate, whereby the AND gate stops supplying output signals. 2-input AND circuits are connected at one input terminal to the outputs of the '1' detector circuits and at the other input terminal to the outputs of the second linear shift registers. The AND circuit connected to the '1' detector circuit supplies the data stored in the second linear shift register to which it is connected. The data representing the quotient of the division .alpha..sup.i -.alpha..sup.j, are delivered through an OR circuit.

Apparatus for dividing the elements of a Galois field

Data representing one element .alpha..sup.i of a Galois field GF(2.sup.m) are stored in a first linear shift register, and data representing another element .alpha..sup.j of the Galois field GF(2.sup.m) are stored in a second linear shift register. 2.sup.m elements of Galois field GF(2.sup.m) are divided into n groups. A table of the reciprocals of n elements located at specific positions respectively in n groups is stored in a converter which includes a decoder and an encoder. The data representing element .alpha..sup.j are supplied from the second linear shift register to the decoder. If the data representing the reciprocal of element .alpha..sup.j are stored in the converter, they are read from the encoder. If they are not stored in the converter, the first linear shift register and the second linear shift register are shifted N times by control pulses generated by a NOR gate and an AND gate until any one of the reciprocal data are read from the encoder, whereby the register supplies data representing .alpha..sup.i+N and the register supplies data representing .alpha..sup.- (j+N). A multiplier multiplies element .alpha..sup.i by reciprocal .alpha..sup.j or multiplies element .alpha..sup.i+N by reciprocal .alpha..sup.-(j+N), thereby performing the division: a.sup.i .div..alpha..sup.j (=.alpha..sup.i-j).

The invention provides a pulse-width modulation circuit in which an output from a latch circuit for holding a count obtained by counting a reference clock signal in accordance with the period of a signal to be modulated is compared by a comparator with an output from a ramp counter for counting the reference clock signal at a predetermined period so as to perform a pulse-width modulation. The number of bits of the comparator and the ramp counter is decreased by n bits with respect to the number N (N&gt;n) of bits of the latch circuit.

Pulse-width modulation circuit

An error correcting system uses an error location polynomial which is defined by double correction BCH codes each consisting of the elements of a Galois field GF(2.sup.m), and thereby generates error locations .sigma..sub.1 and .alpha..sup.2 and error patterns e.sub.1 and 2.sub.2. The system has a first data processing system for performing only addition and multiplication to generate the error locations .sigma..sub.1 and .alpha..sup.2, and a second data processing system for performing only addition and multiplication to generate the error patterns e.sub.1 and 2.sub.2. The first data processing system comprises a syndrome generator, a memory, an arithmetic logic unit, registers, latch circuits, registers, adder circuits and a zero detector. The second data processing system comprises a gate circuit, latch circuits, an arithmetic logic unit, and the registers of a memory.

Error correcting system

A phase sychronizing circuit for a device which reproduces digital data has a phase locked loop including a first phase comparison circuit, a voltage controlled oscillator (VCO) producing an output the frequency of which is controlled by the first phase comparison circuit, and a first frequency divider to divide the output frequency of the VCO. The phase synchronizing circuit further includes second frequency divider for dividing the output frequency of the VCO, a second phase comparison circuit for comparing the phase of a first clock signal from the first frequency divider, with that of a second clock signal from the second frequency divider and a circuit for controlling the frequency dividing ratio of the first frequency dividing circuit according to the phase difference between the first and second clock signals in such a way that the frequency dividing ratio becomes one of 1/N, 1/(N+1) and 1/{(N+(N+1))/2} wherein N is a positive integer.

Phase synchronizing circuit for digital data reproduction

A synchronous circuit comprises a sync signal detecting circuit connected to receive a digital signal with a plurality of frames each consisting of N bits and containing a frame sync signal to detect a sync signal in each frame, and a sync protecting circuit for producing a sync control signal synchronized with the detection of the sync signals and interpolating the sync control signal every frame when the sync signal is not detected. The sync protecting circuit has a counter for counting the number of frames in which the sync signals are not detected. A circuit is provided to quickly synchronize the sync protecting circuit with the detection of the sync signal by the sync signal detecting circuit when noise is produced by the sync signal detecting circuit and then a sync signal is detected after a given value has been counted by the counter.

Synchronizing circuit for detecting and interpolating sync signals

A power-amplifying circuit embodying this invention includes a pre-amplifier stage which comprises two emitter-connected transitors, one of whose bases is supplied with an input signal and an output stage comprising complementary pair of a first transistor of a PNP type and an emitter-grounded second transistor of an NPN type which carry out a class-AB push-pull operation in accordance with the amplitude of a current from the pre-amplifier stage. The power-amplifier circuit of this invention further comprises third transistor for detecting an operating current of the first transistor of the output stage, a fourth transistor which is driven by the third transistor and whose base is connected to the base of the second transistor of the output stage, and fifth and sixth transistors which are connected in such a manner that a sum of the base-emitter voltages of the fifth and sixth transistors is made equal to a sum of the base-emitter voltages of the second and fourth transistors, and through which there flows a current corresponding to a product of the operating currents of the first and second transistors constituting the output stage. A current running through the fifth and sixth transistors is supplied to the pre-amplifier means through a negative feedback path so as to be regulated.

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Kawasaki, Japan

Masahide Nagumo