Matsushita Electric Industrial Co., Ltd.

Masahide Kakeda

Reiji Segawa

A first signal path of a circuit of the present invention is formed by connecting a restricted area in the electrically disconnected state, restricted areas and in the electrically connected state in series, using conductors , and , and contacts and . The circuit is constructed by connecting in parallel six signal paths each being divided by a combination of one or two restricted areas provided thereon. Every time the circuit state is switched, a signal path disconnected by one restricted area is changed suitably to a signal path disconnected by two restricted areas, and vice versa, so as to maintain a signal path disconnected by a combination of restricted areas. By doing so, the switch of the circuit between the disconnected state and the connected state can be repeated an unlimited number of times by a change in one freely-chosen layer.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGN AIDING DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, PROGRAM, AND PROGRAM RECORDING MEDIUM

A first signal path of a circuit of the present invention is formed by connecting a restricted area in the electrically disconnected state, restricted areas and in the electrically connected state in series, using conductors and and contacts and The circuit is constructed by connecting in parallel six signal paths each being divided by a combination of one or two restricted areas provided thereon. Every time the circuit state is switched, a signal path disconnected by one restricted area is changed suitably to a signal path disconnected by two restricted areas, and vice versa, so as to maintain a signal path disconnected by a combination of restricted areas. By doing so, the switch of the circuit between the disconnected state and the connected state can be repeated an unlimited number of times by a change in one freely-chosen layer.

An address translation apparatus comprises: entry storage means for storing a plurality of entries, each entry containing a virtual page number, a physical page number, and a process identifier which is composed of plural bits; comparison information storage means for storing comparison information which defines a method for comparing a process identifier possessed by a process that is currently executed, with the process identifier in each entry; process comparison means for comprising the process identifier possessed by the process that is currently executed, with the process identifier in the entry, on the basis of the comparison information; and entry retrieval means for retrieving, from the entry storage means, an entry including a virtual page number equal to a virtual page number supplied from the outside, and a process identifier which matches the process identifier of the currently executed process, according to the result of comparison by the process comparison means. Therefore, when a physical memory has a content which can be shared between at least two processes, effective utilization of memory area can be achieved by unifying entries with respect to these processes.

Apparatus for translation between virtual and physical addresses using a virtual page number, a physical page number, a process identifier and a global bit

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Takatsuki, Japan

Masahide Kakeda