Mitsubishi Denki Kabushiki Kaisha

Masahide Fujita

Kohji Hashimoto

Katsuya Nakamoto

Hiroyuki Mitsueda

A microprocessor runaway monitoring control circuit with which self-diagnosis of a watchdog timer WDT can be carried out safely and cheaply even during operation of the microprocessor (CPU). A microprocessorsupplies first and second watchdog clearing signals WDand WDto first and second watchdog timers WDTand WDT, and when the both of the watchdog clearing signals WDand WDstop, the microprocessoris reset by way of a logical connector circuit. The microprocessorhas failure diagnosing meanswhich intentionally stops the first watchdog clearing signal WDand diagnoses the response of the first watchdog timer WDTon the basis of a monitor signal MNand stops the second watchdog clearing signal WDand diagnoses the response of the second watchdog timer WDTon the basis of a monitor signal MN, whereby diagnosis of the watchdog timers WDT, WDTis carried out without the microprocessorbeing stopped.

Microprocessor runaway monitoring control circuit

To secure normal operation and then restart a microprocessor (CPU) when a CPU built into an on-vehicle electronic apparatus runs away. A number of on-vehicle loads driven from a CPU, a watchdog timer for monitoring the CPU to reset and restart it on occurrence of an abnormality, and a memory element for storing generation of the reset output are provided, and load driving elements or a load relay is rendered inoperative by output of the memory element. The memory element is reset by cutting off or reclosing the power switch, and an on-vehicle electronic apparatus returns to a normal state.

Vehicle controlling apparatus

An EEPROM write device includes an ECU,A having a microcomputer,A including a CPU,A, an EEPROM,and a boot program,A, and an external write device,A which communicates serial signals SE and SR with the CPU, in which the ECU includes write control means associated with the CPU, the write control means generates a write enable signal to the CPU in response to a receive start of the serial signal from the external write device, and the CPU switches from a normal operation mode to a write mode to the EEPROM in response to the write enable signal, to thereby rewrite the contents of the EEPROM.

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Tokyo, Japan

Masahide Fujita