Nec Electronics Corporation

Renesas Electronics Corporation

Masaharu Mizuno

Naotaka Maeda

Kazuhiro Nakajima

Masahiro Suzuki

Kenji Yamamoto

Shinichi Uchino

Shigeki Sakai

Tooru Fujii

Shigeo Noda

An integrated circuit design method whereby memory instances are assigned to memory macros integrated within an integrated circuit. A plurality of memory instances operating at the same operation frequency are assigned to a single memory macro. A frequency multiplier which receives a first clock signal is arranged to generate a second clock signal through frequency multiplication of the first clock signal, and feeds the second clock signal to the plurality of memory instances. A control circuit which selects the memory instances in synchronization is arranged with the first clock signal.

Method for designing integrated circuit incorporating memory macro

An ASIC includes a function layer formed with plural universal logic cells, a common layer formed with conductive strips connected to the universal logic cells and common to other ASICs and a customized layer having at least two metallization layers assigned to conductive strips extending in certain directions parallel to one another and other conductive strips extending in perpendicular directions to the certain directions, respectively, and an inter-layered insulating layer formed with conductive plugs selectively connected between the conductive strips and the other conductive strips, wherein the conductive strips have respective values of length such that the conductive plugs are located on both ends thereof, whereby the conductive strips, other conductive strips and the conductive plugs form plural signal paths reduced in total contact resistance and parasitic capacitance.

Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign

A universal logic module includes: a first inverter outputting an inverted input signal to an output terminal through a first transfer gate, the inverted input signal having an inverted level of an input signal provided from a first input terminal; and a second inverter outputting an inverted logic signal to the output terminal through a second transfer gate, the inverted logic signal having an inverted level of a first logic signal. The first input terminal is connected to one of a power supply line and a ground line. An input of the first transfer gate is directly connected to the other of the power supply line and the ground line. The first and the second transfer gates are complementarily turned on/off according to a level of a second logic signal. A result of a logical operation between the first and the second logic signals is outputted from the output terminal.

Semiconductor device having universal logic cell

A general-purpose logic cell used in a general-purpose logic cell array for a logic circuit, includes a plurality of kinds of logic circuit elements, each of which has a plurality of terminals with no connection. The plurality of kinds of logic circuit elements includes a flip-flop and a first inverter set. In this case, each of first inverters of the first inverter set is possible to be connected with an input of the flip-flop in parallel or as one of a series connection of at least two of the first inverters. Also, each first inverter is possible to be connected with an output of the flip-flop in parallel or as one of a series connection of at least two of the first inverters.

General-purpose logic cell, general-purpose logic cell array using the same, and ASIC using general-purpose logic cell array

A general-purpose logic cell array includes a plurality of cells and a lower wiring layer. The plurality of cells are formed on a substrate, and each of the plurality of cells includes a plurality of transistors. The lower wiring layer is formed above the plurality of cells, and which connects the plurality of transistors in each of the plurality of cells such that each of the plurality of cells has an elementary logic circuit. Information of the general-purpose logic cell array is provided to a user. The elementary logic circuits may be one of a gate circuit, a selector, an inverter and a flip-flop.

General-purpose logic array and ASIC using the same

A universal logic module that may have a reduced off-leak current in universal logic cells () not used as logic circuits has been disclosed. A universal logic module may include universal logic cells () that may be formed with a second wiring for connecting universal logic cells () from a base configuration formed with a first wiring. Unused universal logic cell () may include transistors in basic cells (A to E) that are non-connected to a power supply (VDD) and/or a ground potential (VSS). Furthermore, unused universal logic cell () may include transistors in basic cells (A to E) that may provide a capacitor between a power supply (VDD) and a ground potential (VSS). In this way, off-leak current may be reduced and noise on a power line and/or a ground line may be reduced.

Universal logic module and ASIC using the same

A general-purpose logic module is composed of: a first inverterin which an input terminal is connected to a first node T; a second node Tconnected to an output terminal of the first inverter; a second inverterin which an input terminal is connected to a third node T; a sixth node Tconnected to an output terminal of the second inverter; a third inverterin which an input terminal is connected to a fourth node T; a first transfer gatein which an input terminal is connected to the output terminal of the first inverter, a first control input terminal is connected to the fourth node T, and a second control input terminal is connected to an output terminal of the third inverter; a second transfer gatein which an input terminal is connected to the output terminal of the second inverter, a first control input terminal is connected to the output terminal of the third inverter, and a second control input terminal is connected to the fourth node T; and a fifth node Tconnected to an output terminal of the first transfer gate and an output terminal of the second transfer gate. Accordingly, it is possible to provide a general-purpose logic module in which a switch can be carried out at a high speed, and a cell using the same.

General-purpose logic module and cell using the same

A semiconductor device includes a plurality of logic cells formed on a semiconductor substrate, wherein each of the plurality of logic cells has a circuit for a function block of a logic circuit; and a wiring layer which connects the plurality of logic cells to form the logic circuit function blocks and thereby the logic circuit. The wiring layer includes a power supply wiring line pattern formed in a region corresponding to each of the plurality of logic cells; a ground wiring line pattern formed in the region; and a plurality of terminal patterns formed in the region. Each of the plurality of terminal patterns is connected with the circuit of the logic cell, and the plurality of terminal patterns are arranged adjacent to at least one of the power supply wiring line pattern and the ground wiring line pattern.

Semiconductor device and manufacturing method for the same

The master slice type semiconductor integrated circuit includes sequential circuit cells ( ) and combinational circuit cells ( ), which are alternately arranged in an inner core area on a semiconductor chip ( ), and a plurality of selective driving elements (MC to MC , MC to MC and MC to MC ), which are connected in a shape of a tree, for selectively distributing a poliphase clock signal for each division area formed by uniformly dividing the inner core area. The plurality of selective driving elements are placed and connected on the semiconductor chip such that load and wiring length between the sequential circuit cells within the respective division areas and input terminals to which the poliphase clock signal is inputted are equal. Due to this configuration, it is possible to cope with a poliphase clock, and also possible to reduce a clock skew between circuits, and further possible to provide a master slice type semiconductor integrated circuit in which an electric power consumption can be reduced.

Semiconductor integrated circuit and its layout method

A general-purpose logic module is composed of: a first inverter in which an input terminal is connected to a first node T a second node T connected to an output terminal of the first inverter; a second inverter in which an input terminal is connected to a third node T a sixth node T connected to an output terminal of the second inverter; a third inverter in which an input terminal is connected to a fourth node T a first transfer gate in which an input terminal is connected to the output terminal of the first inverter, a first control input terminal is connected to the fourth node T and a second control input terminal is connected to an output terminal of the third inverter; a second transfer gate in which an input terminal is connected to the output terminal of the second inverter, a first control input terminal is connected to the output terminal of the third inverter, and a second control input terminal is connected to the fourth node T and a fifth node T connected to an output terminal of the first transfer gate and an output terminal of the second transfer gate. Accordingly, it is possible to provide a general-purpose logic module in which a switch can be carried out at a high speed, and a cell using the same.

Growing community of inventors

Kanagawa, Japan

Masaharu Mizuno