Fujitsu Corporation

Masaharu Maruyama

Toshio Yoshida

Shuji Yamamura

Naohiro Kiyota

Ryuji Kan

Tsuyoshi Motokurumada

Mikio Hondo

An arithmetic processing apparatus includes: an instruction controller; a first level cache and a second level cache. The instruction controller, for a memory access instruction to be speculatively executed that is executed while a branch destination of a branch instruction is undetermined, adds a valid speculation flag and an instruction identifier of the branch instruction to the memory access instruction and issues to the first level cache. The first level cache controller interrupts execution of the memory access instruction when a virtual address of the memory access instruction hits in a TLB of the first level cache, the speculation flag of the memory access instruction is valid and an entry having a virtual address matching the virtual address of the memory access instruction stores a speculative access prohibition flag prohibiting speculative access.

Arithmetic processing apparatus and method of controlling arithmetic processing apparatus

An arithmetic processing device includes: a processor that issues a store command and a load command; and a memory coupled to the processor, wherein the processor: includes a cache memory which stores data to be stored corresponding to the store command and a buffer including entries which stores the data to be stored; searches, in a case where the load command is issued, the entries; and selects, when data to be loaded corresponding to the load command is present in the entries, the data to be loaded from the buffer.

Arithmetic processing device and method for controlling arithmetic processing device

An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area.

Arithmetic processing device, information processing device, control method for information processing device, and control program for information processing device

An address translation buffer of a processor including a memory unit that has a first area with first entries storing first address translation pairs of a virtual address and a physical address corresponding to the virtual address, each of the first address translation pairs is subjected to a index tag which is a part of the virtual address, and a second area with second entries storing second address translation pairs, each of the second address translation pairs is subjected to a whole part of the virtual address, and a search unit that searches the first area for an address translation pair by using a index tag included in a virtual address to be translated, and searches the second area for the address translation pair by using a whole part of the virtual address when the address translation pair is not found in the first area.

Processor and address translating method

An apparatus includes a TLB storing a part of a TSB area included in a memory accessed by the apparatus. The TSB area stores an address translation pair for translating a virtual address into a physical address. The apparatus further includes a cache memory that temporarily stores the pair; a storing unit that stores a starting physical address of the pair stored in the memory unit; a calculating unit that calculates, based on the starting physical address and a virtual address to be converted, a TSB pointer used in obtaining from the TSB area a corresponding address translation pair corresponding to the virtual address to be converted; and an obtaining unit that obtains the corresponding pair from the TSB area using the TSB pointer calculated and stores the corresponding pair in the cache memory, if the corresponding pair is not retrieved from the TLB or the cache memory.

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Kawasaki, Japan

Masaharu Maruyama